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Registered Member #1667
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An efficient step-up converter for 12V battery voltage (11..14V) -> 80V intermediate circuit voltage was needed. This is the first time I did the design for an interleaved booster and I still haven't decided whether the UCC28220 or the LM5032 is better suited for this job. They are both current-mode PWM controllers but the UCC seems to have more sophisticated over- and undervoltage inputs - it does, however, not feature integrated gate drivers.
The on-chip oscillator runs at roughly 100 kHz, generating 50kHz operating frequency for each phase, design parameters are 80V 0.75A (edit! of course it is amps...) output with <0.5V ripple. I copy&pasted the low pass feedback loop of the rail-to-rail opamp from a design example. The roll-off in the bode plot will have two knees and my interpretation of the feedback loop is "just filter out the 100kHz oscillator frequency". The feedback loop is designed for 250-500kHz operation but I don't think the values are that critical.
I know it's a lot to ask for.. but did I do something wrong? I did this design for a friend and I won't build the converter myself any time soon. Thanks in advance!
Registered Member #1667
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ok, I found the first mistake: S1 needs to be connected to IC1.Pin2, I changed the opamp to LM8261 after including the switch which had worked fine with an LM393...
Registered Member #1232
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> The roll-off in the bode plot will have two knees and my interpretation of the feedback loop is "just filter out the 100kHz oscillator frequency". The feedback loop is designed for 250-500kHz operation but I don't think the values are that critical.
You might be in for a surprise then! The component values in the feedback path are for control-loop compensation. They are often quite critical in order to keep the supply stable over line and load variations, ...and they almost always depend on the switching frequency for a switched-mode power supply.
Feedback compensation for a boost converter is a big topic and can get quite complicated. All I will say is that you need to work out if the boost converter works in the continuous-current mode or discontinuous-current mode first. If the inductor current is discontinuous there is no right-half-plane zero and the loop compensation calculations are slightly easier. This is usually the case for low-power converters. However...
If the inductor value is larger and the current is continuous at full load then there will be a right-half-plane zero in the open-loop transfer function for the power stage, and control loop compensation becomes something of a challenge! This situation is more common for higher power converters where the ripple current is kept small for efficiency or EMI improvements. The downside is a much harder control loop design and degraded transient response.
Registered Member #1667
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Thanks Richie, seems like things will get really serious with the feedback loop since I have a resonant output filter. I found the design guidelines briefing here:
I hope I'll get this managed in some way. Just one more question: the briefing states that "for synchronous and non-synchronous buck converters, the bandwidth should be between 20 to 30% of the switching frequency." - for interleaved converters, do I have to take the single phase switching frequency or rather the original oscillator frequency?
ps. the briefing deals with single phase buck converters but type II and III compensation networks don't appear to be specific to any topology. However, I can't find information on multi-phase converters. Here's another article about feedback networks,
Registered Member #1232
Joined: Wed Jan 16 2008, 10:53PM
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the briefing states that "for synchronous and non-synchronous buck converters, the bandwidth should be between 20 to 30% of the switching frequency." - for interleaved converters, do I have to take the single phase switching frequency or rather the original oscillator frequency?
You take the operating frequency of one single boost converter. Each boost converter essentially operates in isolation so the overall bandwidth is limited to about 1/5 of the switching frequency of each boost converter. The system clock may well run at twice this frequency, and the ripple current through the output capacitor may be twice this frequency too for a two-phase interleaved design, but the bandwidth is still limited by the stage switching frequency.
Both of the documents you linked to are good, but they may not be applicable to current-mode boost converters. Whilst the first document gives a good account of type-2 and type-3 compensation for a voltage-mode buck converter, the boost converter is a different beast. The second document is more applicable to the voltage-mode boost converter as it discusses the two modes of operation (discontinuous current and contuninuous current.) It also gives a good account of the Right-Half-Plane zero phenomenon, what it actually means in practice, and how to work around it.
I wouldn't worry too much about your converter being a poly-phase interleaved design, because it won't change the maths that much. If you can get it working with one boost converter first and it is unconditionally stable, then it should be two hard to get the two converters working interleaved.
Registered Member #1667
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mh, just a thought: why do I need fast response, anyway? I might as well design a feedback loop for as low as 1 kHz or even 100 Hz. I could compensate for that with larger output capacitors so the argument for more bandwidth is just that one needs just enough capacity to have the ripple voltage covered?
ps.I bet the feedback compensation won't work at all, I've even missed two diodes in series... ah well, a strong low pass will cause overshooting, right?
Registered Member #1667
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ok I better throw the feedback section in the dustbin. Does this look any better?
This feels like a waste of time because there is still the output filter network with its ringing at some 100 Hz to 1 kHz and this isn't covered by all the approximation formulas I could find. So it is trial and error yet again?
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I'm also working on a boost converter to feed my 100W led. The thing that I like to do is use a AVR to provide change the duty cycle. This allows you to experiment with the control loop and makes it easy to adjust for any mistakes you might run in to. Think I'll have a look at the math after a real control loop here. Nice to practice for my exam in control loops
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that sounds quite interesting! I'm still having a hard time understanding what exactly makes the whole system unstable. The output filter I use has a resonance frequency that is really low. I found a nice approach to understand the transfer function graphically Let's see if I got things right... One uses exp(i*(2*pi*f0)*(1/f)) to look at the spectral response (amplitude only). The amount of attenuation translates into a finite distance of the poles from the unity circle, however approaching a pole means getting close to a possible resonance. right half-plane (positive real part) means the amplified output of the open-loop system is in phase with the input and closing the loop would result in ringing, hence the instability of the regulator. Pole zero cancellation means putting a zero close to a pole and hope that the zero order radial moment vanishes, creating some higher order radial moments (expecially a dipole moment, just thinking of spherical multipole expansion). The closer a pole is to the circle, the more difficult it gets to cancel it within electronics tolerances.
So basically I'm looking for a feedback network that creates -90..-180 deg phase shift until 0dB amplification is reached, right? Type II and III networks introduce a phase boost to ensure the total feedback is still negative over the whole range where there is a gain factor above unity. The last thing to look after would be the feedback bandwidth. I just analysed a "fool-proof" single phase power supply and found the -3dB point to be around 250 Hz (switching frequency is 23 kHz). As I will be using the converter with medium sized output capacitors, AC load regulation is not my No.1 concern, I bet the whole trick is just to stay well above the LC-Filter resonance as to flatten out its ringing.
I am not seriously into using textbook design guidelines so instead I try to understand what the requirements are and find a solution, either experimentally or by some calculations that satisfies them, if nothing works it is just because of my foolishness
Registered Member #30
Joined: Fri Feb 03 2006, 10:52AM
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hboy007 wrote ...
mh, just a thought: why do I need fast response, anyway? I might as well design a feedback loop for as low as 1 kHz or even 100 Hz. I could compensate for that with larger output capacitors
That is one recommended way (certainly for hobbyists) of dealing with the right-half-plane zero. Just slug the cr@p out of your feedback loop. If you go this way, you have to get your loop gain below unity before you get to the output filter's resonant frequency, because its phase lag quickly heads towards 180 degrees above this frequency, and your slugging capacitor adds another 90 degrees lag.
Another way is, rather than slugging the response, just lower the gain of the error amp to 100 or 10 or whatever. This does the same as slugging but without the 90 degree lag, so there's a greater stability margin.
The classic series RC compensation network you see slung around a SMPS error amp can be set up as a combination of the above. You have high DC gain to get rid of the DC error, then the gain goes down at 6dB/octave, then finally the resistor flattens the gain off, getting rid of the phase lag before the output filter gets to 180 degrees. But the RHP zero can mess this scheme up.
Yet another way I've used is to feed a small sample of the inductor current into the feedback loop. If you feed in enough, it cancels the RHP zero, giving great stability and transient response, but it adds an "IR drop" type of error to the output voltage.
This saved my day in a commercial design I was working on, where the converter was going to be post-regulated, so the error wasn't important. I think it was actually GeordieBoy who suggested it to me.
I think the LM2586 does this internally, with some patented way of geting rid of the DC error.
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