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small signal equivalent circuit of MOSFETs

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LAN_403

the_anomaly

Thu Mar 11 2010, 03:37AM

Registered Member #19 Joined: Thu Feb 02 2006, 03:19PM
Location: Jacksonville, FL
Posts: 168

I am having some trouble understanding the ac equivalent circuit of a common source n channel mosfet amplifier. See page 4 of this powerpoint:

why is the resistance of the output g(d) in parallel with the voltage dependant current source and not in series. All the descriptions I have found say there is a resistance involved in the equivalent circuit because a mosfet has a finite resistance when in saturation. Why is this resistance not in series with the current source?

Henry H

Thu Mar 11 2010, 03:53AM

Registered Member #2298 Joined: Sat Aug 15 2009, 08:16PM
Location: ex UK, now Santa Cruz, CA
Posts: 35

not too confident on this, but I think it's because of the representation as a current source. If the resistance were in series with the current source, no effect would be seen at the D and S terminals. By analogy imagine an ideal voltage source in a black box with a resistor in parallel with it. The resistor has no effect on the output voltage. Similarly a resistor in series with a current source has no effect on the output current.

radiotech

Thu Mar 11 2010, 04:08AM

Registered Member #2463 Joined: Wed Nov 11 2009, 03:49AM
Location:
Posts: 1546

Could it be g(d) is a conductance and not a resistance. On page 3 it comes from Id/Vds.

Mattski

Thu Mar 11 2010, 05:14AM

Registered Member #1792 Joined: Fri Oct 31 2008, 08:12PM
Location: University of California
Posts: 527

If you plot the I-V curve for a MOSFET then as you increase the drain-source voltage, the current will increase. For a very ideal device we would hope that this is small, so the IV curve is pretty flat once you get above the threshold voltage. It is modeled as a conductance, so the slope of the increase is 1/g_d.

It is basically a parasitic path where current can flow when you put a voltage from drain to source. If that path were not there then the device would be ideal, and as you change Vds you get no change in current. It is also referred to as R_ds sometimes, which is 1/g_d depending on if you look at it as a resistance or conductance.

the_anomaly

Thu Mar 11 2010, 02:11PM

Registered Member #19 Joined: Thu Feb 02 2006, 03:19PM
Location: Jacksonville, FL
Posts: 168

Thanks for all the info. I think I found the answer. Begin with this common source circuit:

Small Ac 1

We want to know the small signal voltage output at v_o. Thus we use Thevenin analysis. All independant voltage sources go to zero and in order to do that we draw them to ground (short circuit them).

Small Ac 2

We can now redraw the circuit with R_D connected to the source ground as such:

Small Ac 3

Now we have completed Thevenin analysis and ended up with a Norton equivalent circuit.

Steve Conner

Thu Mar 11 2010, 02:22PM

Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706

That's basically it. A resistance in series with a current source has no meaning, because an ideal current source outputs the same current irrespective of the load. It has to be in parallel to have any effect on anything.

And being a small signal model, it can't handle the concept of saturation. Small signal models are only valid for small changes around the operating point where you extracted the parameters.

Case in point: When you use Spice to do an AC analysis of a circuit, it first does the DC bias point analysis, and uses the voltages and currents from this to determine values of gm, etc. for its small signal equivalent models of transistors and so on. You can easily get an output of 1 million volts in AC analysis mode, from a circuit running on 5 volt rails, because the models are linear.

If you want to see the non-linearities, you have to run in transient mode, where it uses different models that are valid for large signals too. And much more computationally intensive, so you have to wait longer for the answer.

Dr. Slack

Thu Mar 11 2010, 02:39PM

Registered Member #72 Joined: Thu Feb 09 2006, 08:29AM
Location: UK St. Albans
Posts: 1659

Well that transformation is not strictly it, because you have ended up with the drain resistor from the external circuit across an otherwise ideal FET output. While this is correct, it doesn't tell you anything about the FET intrinsic output resistance.

The point is that the FET output has an impedance, and can deliver power into a load. When doing small signal analysis, this can be modelled as either a voltage source in series with the impedance, OR a current source in parallel with the impedance. The choice of representation is entirely up to the engineer, the FET just does its impedance and power thang regardless.

The choice of which representation to use boils down to which is more convenient to use, which results in more sensible values, which has more history behind it, but most of all which is closer to the truth. In this case, both bipolars and FETs are *almost* ideal current sources over a large range of parameters, so using a current source rather than a voltage source as the basic model is a no-brainer. For many low-accuracy applications, the impedance can be replaced by infinity, which is then omitted. If we used a voltage source model here, then we'd need a very high voltage source, through a very high resistance, and both parameters would have to be linked by the current they could source into a short circuit to make it meaningful; very inconvenient and non-physical, but strictly mathematically correct and useable.

Now that the FET output is modelled by a current source, the output impedance (when needed for very accurate modelling) *must* be in parallel, because as several other posts have pointed out it wouldn't actually do anything if it was in series.

Unless you are really pushing it and relying on a very high output impedance, then you can neglect the output impedance and call it infinity. As far as the signal gain is concerned, the output impedance ends up in parallel with the external drain resistor, so simply results in a slightly lower gain than expected.

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