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Registered Member #1488
Joined: Sat May 17 2008, 10:41AM
Location: Germany
Posts: 18
Hi, i am trying to build a SLR Capacitor charging power supply for charging a 12µF 1600V capacitor with a high repetition rate from rectified mains or similar. So far the Contrlol logic consisting of ne555 + Logic Gates + Discrete Gate drivers is finished (prototype). i intent to go for a resonant frequency of about 50KHz. The H-Bridge is build of 4 IRG4PC50F IGBTs (+ STTA5 Freewheeling diodes) which actually are intended for hard switching only up to 5KHz and over 20KHz for Resonant switching (from Datasheet). So i thought they should be ok. The problem now is, that when bringing switching speed to where i would think it should be ( about 200 nS Rise-Time ) the Gate signal looks fine with no Voltage over the Bridge and starts to show lots of ringing at about 60 MHz at the gate and Switches-Midpoint when votage is increased.
The GDT i use has leakage inductance of about 350nH and 7 Turns driven from a fullbridge of irf530/irf9540 and 15V. Here are pictures 1st: Gate waveform with 10 Ohm gate resistors at each gate and bridge voltage of about 60 Volt and no Load. 2nd Gate Waveform with 10 Ohm at each gate and 10 Ohm in series with the primary of the GDT.
The ringing at the Gate in the first picture really looks nasty so i tried making a better gate drive Transformer with less leakage but didnt manage do get it lower than 300nH even with screened cable. this is most likely due to the cores i use which i mostly have no idea what material it is. What the heck i thoungt, just build 4 discrete buffers in front of each gate to decouple the leakage inductance from the gates to get a lower drive impedance.
even with no additional Gate resistance there was no ringing at all without voltage at the bridge and rise and fall-times of about 70nS. Applying voltage again ruined everything, the spikes were even higher now due to the faster switching speed. Adding resistance again made it better but then the advantage of the low drive impedance to stand against the evil miller effect (which i think is the cause of all this misery) would be wasted. Even adding additional capacity directly to the gates didn't bring much besides wasting lots of energy so my question is would it be better to go for the clean signals an low speed switching or better ignore the ringing (can easily be supported by pressing the 20 MHz filter button at my scope) or looking for further improvements in the gate drive? Or maybe these igbts are not worth the effort and i should go for something faster with less output capacity? Here is a picture of the core i want to use for the HV Transformer (the primary seen is only for testing.
And maybe someone cares what i want to use the Power supply for:
This is part of a pulsed HV Power Supply from a Excimer Laser which i found at the junk yard. First pic shows the arrangement of the Tank capacitor and the second pic shows the partly disassembled output Pulse Transformer which originally had a step up ratio of 14. In the bottom of the last picture the main magnetic switch can be seen which is quite hefty and havy. The output pulse most likely had a length in the order of 200nS. there was another HV pulse-compressing stage which i do not yet intend to use because i do not really know what to do with the whole thing anyway (besides having fun).
Thanks for reading this, maybe someone has a few tips for me how to proceed.
Registered Member #1451
Joined: Wed Apr 23 2008, 03:48AM
Location: Boulder, Co
Posts: 661
I made a small SLR inverter with MOSFETs. This did it for me: no resistance at all at the gates but a small amount (like 6 ohms) on the PRIMARY side of the GDT. My signal went from a large amount of ringing to almost none at all.
Registered Member #1488
Joined: Sat May 17 2008, 10:41AM
Location: Germany
Posts: 18
Hi again, thank you for the answer, that i tried already but there was not so much difference at all in changing the resistance from the secondary to the primary although it seems i need somewhat less resistance to achive the same amount of ringing with faster switching when putting it to the primary.
Knowing already the good work from Marco Denicolai with his ccps from his Thor Project i checked again his Website and found this where in chapter 5.3 there are exactly the problems addressed which i seem to have too.
He writes that the emiter stray inductance is the main cause of the ringing by building a resonat circuit with the IGBT internal capacity. I do not understand this because than the ringing should be there even without any voltage transient at the collector. In my understanding this emitter inductance should be in series with the gate driving inductance and so should be part of the cause for the ringing one sees with no gate resistor. Otherwise i would think there would be no need for the ringing to start at the beginning of the miller plateau.
On the other hand he writes that the emitter inductance causes negative feedback between gate voltage and emitter-current which is very logical, but by my understanding this should not be measurable at the outer connectors of the igbt as a lower voltage at the gate (or as ringing) because the votage drop would be completely internal. Although it surely might cause the igbt to swich off again and therefore is quite dangerous. So by my understanding (which of course could be completely wrong) the best way to get the igbt to switch with lowest losses would be to provide it with a low impedance drive signal (as low as possible) with adjustable slope. Maybe someone could give me a hint if i am missing something here,
Registered Member #162
Joined: Mon Feb 13 2006, 10:25AM
Location: United Kingdom
Posts: 3140
AFAIK the problem with making big igbts go fast is not a gate-drive problem as such, it's the 'tail' current not reducing quickly enough - causing shoot-through. A quick look at the datasheet: Total switching loss 5mJ @Tj=150C. x50kHz=250W= I realise that you'll be using lower collector current and better gate-drive than the spec.sheet example, but you'll be pushing them hard. It's 'nice' to have clean gate-switching waveforms but the collector current waveforms are I think more important, so if they're ok you're done..
For hobby use I like to consider what will happen when one of the igbts goes short... the gate drive circuitry gets a short to the dc bus via the other igbt in the bridge. (e.g. low-wattage gate resistor or thin wire, gate-clamping diodes etc.) Makes replacing blown up bridges less painful.
Registered Member #1488
Joined: Sat May 17 2008, 10:41AM
Location: Germany
Posts: 18
Hi, thanks for the reply. i had hoped that the tail current would be less of a problem in this circuit because there is about 50% dead time involved and the switching accures at zero current anyways, so there should be nothing to hold any tail current up. The switching losses of 5 mJ are for hard switching 39 Amps with 480V DC-Bus at 150°C, i hope that this will be completely different here. Being a little bit worried anyhow i made some tests with low voltage and high current. Therefore i had to rewind my transformer to have the secondary directly across the primary to decrase leakage inductance (2µH now). Together with a 2.2µF Cap i get the IGBT to its max current even with low voltage. Now i watched the temperature of the cooler when changing from soft switching to hard switching of about 40 Amps.
It really is a big difference, with soft switching there is quite a bit heat production but this increases dramatically when doing hard switching. switching 40 Amp witch 1.5V at the IGBT produces an average of about 45Watt in the bridge (the diodes have a seperate cooler) so i think the heat when softswitching is nearly completely due to these conduction losses (at least i hope so).
I do not completely understand what you are saying about the gate drive being shorted to the dc bus. If one igbt dies shorting the secondary of the GDT, i would hope that this would protect the bridge by preventing the other IGBTs to be switched on over the shorted GDT. But i most certainly will see if this is so in the near future. Till now only one of the Freewhelling diodes died at the high current testing because i had not provided enough cooling for them.
Registered Member #1488
Joined: Sat May 17 2008, 10:41AM
Location: Germany
Posts: 18
Hi, concerning switching losses, i have no direct way to measure them, but a comparision between hard switching and soft switching by simply measuring the temperature of the cooler should give some idea, first i tried to let it run at 40 amps hard switching, but with time and no forced air cooling the temps were fast rising above 100°C wich got me worried so i reduced it to 20 Amps peak and switching directly at the peak. Within about 20 minutes the temp stabilised at about 94°C, getting back to soft switching and waiting even longer it got to about 73°C, so the difference is not as dramatic when measured versus touched but still conciderable when keeping in mind that the supply voltage was only about 20Volts so i think that with a 400VDC bus it would be impossible for the bridge to survive hard switching then with the actual cooling. Conduction losses on the other hand should not change at all. With soft switching of 40 Amps max the diodes are getting too hot again with time (more then 110°C)
This is a pic of the primary Voltage (across the Primary of the Transformer) and the current with 20 Amps peak and voltage being 20Volts peak.
Registered Member #1488
Joined: Sat May 17 2008, 10:41AM
Location: Germany
Posts: 18
Hi, the inverter works good now, but whats still missing is a way to regulate the output. A search for this didnt provide much. I dont want to just switch the Inverter off when the desired voltage is reached, but want a real gegulator. As i understand it, introducing PWM will distroy ZCS operation, so i thought i need sometihing that creates complete cycles but changes the dead time according to power need. The circuit i made for it so far consists of 2 non-retriggerable Monoflops in Series where the first creates a pulse as long as one complete cycle takes and the second one creates the drive signal. In the End i can regulate the density of the pulses with the input frequency While the first Monoflop makes sure that frequencys higher than the maximum usable do not interrupt the actual cycle.
i use hcf4098be Monoflops for this, not the ones shown in the picture
All that is left now is a VCO and some opamps to close the regulation loop.
Still, i think there will be some problems with the stability of the loop because the frequency can drop very low if a big dynamic range is wanted, so at low load or low voltage it could get difficult du maintain stability.
Maybe someone has given such a controll scheme some thought already or can give some hints. The biggest question is if such an approach has any advantage at all?
Registered Member #205
Joined: Sat Feb 18 2006, 11:59AM
Location: Skørping, Denmark
Posts: 741
Peter,
A good way to regulate is this: Have an oscillator to produce main switching frequency, and generate gate signals. Implement gate drive trough enable pin of gate driver chip. Syncronize gate drive signal to edges of gate oscillator output, so that you never start or shut down bridge in mid cycle.
Use resistive/perhaps capacitive voltage divider to monitor load voltage. (you are chargign a cap, right?
Set comparator with *enough* hysteresis, to stop oscillator when voltage is high enough.
Registered Member #30
Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706
Yes, the SLR is difficult to regulate, and the way you're doing it is the best way I know of.
For this reason, the current source inverter is often used instead of the SLR in industry. You regulate a CSI by controlling the DC link current with a separate buck converter. That doesn't work so well with the SLR because it's a voltage mode circuit with a big DC link capacitor.
But for DIY capacitor charging the SLR should be more than good enough: just turn it off when the capacitor gets full.
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