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FWCW HV Multiplier: Optimal Capacitor Arrangment / Protection

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LutzH

Thu Jan 07 2010, 06:46AM

Registered Member #1721 Joined: Sat Sept 27 2008, 08:44PM
Location:
Posts: 136

Hello:

I cannot seem to be able to come up with a clear solution to a voltage multiplier design problem, in part because the VM simulation software that I found, in addition to the formulas which I have, are all for the same capacitor value, in each stack?

I want to use two different values of capacitance, for more efficient stage charge transfer, actually 3 values, including the 2 larger input capacitors. This is simply a better way to build a voltage multiplier, but it is difficult to find any design literature about it. I have worked out most of the issues involved, and I have researched the protection aspects of voltage multipliers extensively. The issue on how to exactly optimally arrange the different value capacitors, in the multiplier stack, for the greatest benefit, still eludes me. I have however narrowed it down to two basic configurations.

I also went with 2 extra stages due to them being required, because of the effect of stray capacitance on the voltage buildup, and its resulting losses, per my calculations, or better said estimate :) I realize that the voltage here is well above what most folks will want, but the design, and the protection considerations, are the same as they are for lower energy 120KV multipliers for example. So the value of the design work, will apply to a 120KV multiplier, just the same, which is why I feel it is worth posting. Just remove one zero :)

Here is the background:

Stages = 12

Design = FWCW Multiplier

Stage Voltage = 80KV (40KV + 40KV Input)

Frequency = 20-30KHz

Output at 800KV = 2ma

Capacitors:
Cap Type 1 = 100KV 455pF (2 910pF 50KV Caps in Ser.) 12 Available
Cap Type 2 = 100KV 850pF (2 1700pF 50KV Caps in Ser.) 32 Available
Cap Type 3 = 80 KV 2000pF (2 2000pF 40KV Caps in Ser) 4 Available

Diodes = 2CL2FM: 20KV / 100-200ma, <100nS, SCSR = 10A (6 in series for each leg = 120KV, x 4 for each stage) The first and last stages having 2-3 times the total number of diodes in parallel for an increased surge protection to 20 - 30A peak.

During a discharge, these 2 stages see the greatest surge current. When an arc occurs the AC stack discharge path is through 22 of the 24 AC stack resistors, and through the top and bottom diodes. My question here is: What if I increase the inter-capacitor resistor value to 4K ohm, or even 8K ohms, instead of 2K ohms? Could I then save on diodes, or will this mess up the charge transfer some how? With an input voltage of 40KV, 4K, or 8K ohms this would still support a current flow of 5-10 amps, so on the surface it would seem that this is no problem, and the way to go. I have however learned that at 20-30KHz this may not be the case, maybe it would cause havoc with the potential distribution or something?

Resistors = 2K-4K ohm, 5W resistor strings, between each cap, in each stack. All in series with the capacitors of each stack. My protective resistor value calculation is: 12 Stages: 800KV / (24 x 2000 ohm) = 16A surge.

Also in the circuit are 2 Input protection resistors, and several protective spark gaps.

The FWCW multiplier has 3 total capacitor stacks, the two outside AC stacks, and the center DC stack. I am looking at 2 possible options for arranging the different value capacitors:

Option 1:

All 12 stages of the center DC stack capacitors, being of the lower value Type 1: 455pF capacitors. The first 6 stages of the two outer AC stacks, being the higher value 850pF caps (Stages 1-6 from the bottom input end.) The next 6 stages being only of the lower value 455pF caps in all three stacks, (Stages 7-12). Here the center DC stack would be 12 of the 455pF capacitors only. Each of the two AC outer stages would have 6 850pF capacitors in the first 6 stages followed by 6 stages of the 455pF capacitors. Since only the 2 outside AC stacks transfer the power in a FWVM, it would seem like this is the best way to go for power transfer efficiency, since the center stack is just storage/ a filter in essence?

Option 2:

All three stacks all having 2 different value of capacitors. The lower 4 stages of all three stacks, being only of the higher value 850pF capacitors. The upper 8 stages would consist of the lower value, 455pF capacitors, in all 3 stacks. Here each individual capacitor stack would have 4 850pF caps on the bottom, followed by 8 455pF caps.

I thought about putting only the higher value caps in the center DC column, and then putting the remaining higher value ones, in the lower stages of the outside AC stacks. This would however result in a lower charge transfer efficiency per my calculations, so I settled on the two above options. I do not care about the ripple as much as the charge transfer efficiency. In a nutshell I want the least possible voltage drop when HV current is drawn from the top of the stack. Any help with this would be greatly appreciated.

Note: I do realize that the first 2 input outer AC stages see only the input voltage, and not 2 x the input voltage like all of the other stages. So I plan to use two 80KV 2000pF caps for these first 2 input stages. Each unit being two x (2) 40KV 2000pF caps in series for each one. This is probably very simple to figure out, but I am just not confident in my choice between these 2 options. I do realize that most VM designs do not use different value capacitors, but only in order to keep things simple. The down side to doing it this way is that it is simply not as efficient, and it requires larger capacitors, for the same current which is very expensive, in addition to not being a "clean" design. Thank you in advance for any ideas, or thoughts, which you may have to offer on this subject.

Thank You........Lutz :)

Wolfram

Thu Jan 07 2010, 08:57AM

Registered Member #33 Joined: Sat Feb 04 2006, 01:31PM
Location: Norway
Posts: 971

There is some relevant information here

and here

. There might also be some information of use here

and here

.

Check out LTSpice for simulating it, it has worked very well for me in the past.

Anders M.

Proud Mary

Thu Jan 07 2010, 10:54AM

Registered Member #543 Joined: Tue Feb 20 2007, 04:26PM
Location: UK
Posts: 4992

Multiplier Design.xls is an Excel Spreadsheet VM calculator:

LutzH

Fri Jan 08 2010, 01:18AM

Registered Member #1721 Joined: Sat Sept 27 2008, 08:44PM
Location:
Posts: 136

Hello:

Thank you for the help, when reading the replies I had to chuckle and smile, because the exact references posted, were the reason that I choose to use different value capacitors to begin with :)

What I especialy liked about what this guy in Germany did, is all of his wonderful experimental work which was done to confirm, and to test, his theories on VM construction. One can say for sure, that he used the scientific method very well.

Of all the amature VM work that I have have seen, this guy gets my gold medal for VM stack design work. On the driver end Steve Ward, and his HF work, gets the Gold for driving a stack.

I would like to borrow from both of these fellows by building a VM stack based on the German guys principals, but driven by a Steve Ward inspired IGBT HF driver.

I will check out LTSpice on the net, if it allows me to enter different value capacitors in the same stack simulation, then it could be just the ticket. Thanks for the tip.

Other than the actual construction, I still would like to see if I can reduce the stray capacitance as much as possible. I do not really have a clear understanding of the exact sources of stray capacitance in a VM stack, other than the charges between components. I am trying to use contruction materials with a low dielectric constant when possible in maybe a futile efort to keep it down, like polycarbonate instead of glass fiber products ect. For now its on to LTSpice, thanks.

Aloha.....Lutz :)

Proud Mary

Fri Jan 08 2010, 01:35AM

Registered Member #543 Joined: Tue Feb 20 2007, 04:26PM
Location: UK
Posts: 4992

Journal of Electron Microscopy 43(1): 25-31 (1994)
Â© 1994 Oxford University Press
A Numerical Analysis Approach to Cockcroft-Walton Circuit in Electron Microscope
Haibo Zhang, Akio Takaoka and Katsumi Ura*

*Department of Electrical and Electronic Engineering, Faculty of Engineering Osaka Sangyo University, Nakagaktuchi 3-1-1, Daiiou, Osaka, 574 Japan
Department of Electronic Engineering, Faculty of Engineering, Osaka University Yamada-oka 2-1, Sulta, Osaka, 565 Japan

A brief survey is given on the conventional methods of analyzing a Cockcroft-Walton (CW) circuit. It shows that these methods are not suitable for analyzing the surge and ripple performance. Thus this paper proposes a numerical approach to the CW circuits in electron microscopes (EM). In this approach, taking advantage of the cascade connection, we formulate the state equations of a CW circuit having arbitrary stages. The Gear's algorithm is used to solve the state equations numerically, overcoming the nonlinear stiff problem and obtaining accurate solutions effectively. As an example to confirm the effectiveness of the approach, we simulate the surge current and ripple voltage in the CW circuit for an ultra-High Voltage EM (ultra-HVEM) by using a supercomputer.

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