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Proper selection of bypass capacitor values

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IamSmooth

Sun Dec 13 2009, 12:49AM

Registered Member #190 Joined: Fri Feb 17 2006, 12:00AM
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Posts: 1567

I am driving a gate transformer with my inverter using the TC4421 and TC4422 gate drive chips.
chip specs

On page 9, section 3.1 it says a minimum of 1.0uf is suggested, and the value is based on how much of a capacitive load is being driven. On page 10 there is a diagram showing a 0.1uf and 4.7uf capacitor in parallel.

My questions are:
1. what is the purpose? I thought it was to prevent voltage spikes on the supply line.
2. how does one determine the proper value?
3. if the load is alsmot all inductive, will 1.0uf suffice, or should I have a 0.1uf and 1.0uf capacitor?

Sulaiman

Sun Dec 13 2009, 02:01AM

Registered Member #162 Joined: Mon Feb 13 2006, 10:25AM
Location: United Kingdom
Posts: 3141

For TC4421 etc. if the supply bypass capacitor is 10x the output capacitor you could expect about 10% dip in the supply voltage during switching, because the charge delivered to the output capacitance will come mainly from the bypass capacitor, due to the inductance of the supply line(s).
This explains why bypass capacitors have to be physically close to the device they are bypassing.
Different types and values of capacitor behave differently with pulses, generally electrolytics are slow and ceramics are fast, hence the use of 0.1 uF ceramics.

At very high frequencies the internal construction and even the lead-length of capacitors can be important.
So
Q1) what is the purpose? I thought it was to prevent voltage spikes on the supply line.
A1) The main purpose is to 'hold up' the supply when current pulses / 'spikes' are taken from the supply.
When a significant current is being drawn from the (inductive) supply line then suddenly stopped, there will be an inductive flyback-type voltage spike, bypassing is also to absorb this energy.

Q2) how does one determine the proper value?
A2) start with 10x or more the output capacitance then 'scope the working circuit, if voltage spikes (positive or negative) are large then increase the capacitance.

Q3) if the load is alsmot all inductive, will 1.0uf suffice, or should I have a 0.1uf and 1.0uf capacitor?
A3) many devices take short high current pulses from the supply when switching, even with no output load, due to the internal circuitry ('shoot-through'/'cross-conduction') so it's ALWAYS a good practice to provide sufficient bypassing.

Mattski

Sun Dec 13 2009, 04:11AM

Registered Member #1792 Joined: Fri Oct 31 2008, 08:12PM
Location: University of California
Posts: 527

The reason for having multiple capacitors in parallel instead of a single bypass cap is that in general smaller capacitors are better for fast response (lower ESL, ESR), and larger capacitors are slower but have more energy so they can handle longer or larger transients. Also, surface mount is better because they don't have the inductance of the leads adding to ESL.

All of the theory has to do with RLC circuits, which is simple. But in practice it is complex, since it would involve modeling your supply line traces, ground connection, knowing pretty accurately what the current pull of the device looks like. Then you would specify a maximum voltage ripple. It's pretty involved, and modeling the capacitors themselves takes a bit of work, so it's not uncommon to just follow rules of thumb, and you can get those from either doing modelling, or building it and seeing if it works or not.

What I would do is make your board, and leave room for a few capacitors from 0.1-4.7uF. Try out a 0.1 and a 1uF, then if you have too much ripple, switch the 1uF for bigger one, or maybe add a second 1uF in parallel. Or maybe it will work fine, so take out a capacitor and check again. Eventually you'll find a good combination.

mikeselectricstuff

Sun Dec 13 2009, 10:45AM

Registered Member #311 Joined: Sun Mar 12 2006, 08:28PM
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Posts: 253

With the advent of cheap high-value SMD ceramics, it is less necessary nowadays to use multiple caps for decoupling - a single 4.7uf ceramic would suffice for all but the very highest frequency (100s of MHz) apps, where small inductances become more important - even then this is more about physical size and board layout than the characteristics of the cap itself.
The only thing to bear in mind is that cearmics whose dielectric type contains a 5 (e.g Y5V) can suffer significant reduction of capacitance over voltage and temperature.
My 'default' logic decoupler nowadays is an 0805 1uf X7R, which generally avoids the need for additional bulk decouplers.

radiotech

Sun Dec 13 2009, 07:36PM

Registered Member #2463 Joined: Wed Nov 11 2009, 03:49AM
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A3. Electrolytics are made with a coiled plate structure in many types.Intrinsic inductance could cause heating if there is energy in the applied voltage spectrum at frequencies where the reactance will cause enough voltage across the length of those coils to heat them by I^r losses. The 0.1uF will snub
these high frequency voltages. There is a family of SCR rated capacitors made to avoid this. The old Dynaco 120 amplifier kit asked builders to wind a coil around the electrolytics in a direction counter to the plate winding to improve high frequency performance.

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