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Registered Member #84
Joined: Thu Feb 09 2006, 01:06PM
Location: Dallas, TX
Posts: 47
I see Comms analog to digital converter spec sheets with RMS jitter in the 80fs range.
(80fs) (80fs) (60fs)
How do these guys get such low jitter and consequently such low phase noise? Are there any commercial systems out there that are able to beat these numbers? I assume something would have to be better than 60fs to be used to test a 60fs device.
Registered Member #56
Joined: Thu Feb 09 2006, 05:02AM
Location: Southern Califorina, USA
Posts: 2445
I am using a setup at work that measures lifetimes on the order of 100fs, but I am using an optical down conversion method which I don't think would work to well for this application...
I suspect that the number is derived by some means of down conversion, probably by looking at a digitized waveform at a GHz, fitting the points to a true sine wave, and looking then comparing the theoretical time axis with the measured one, or some such method. Any variation in the sample time/length would show up in such an analysis, with with a 100db snr you should be able to get some very small numbers out of it.
I will say, low tens of fs seems really quite tricky to measure! Here I thought the hundreds of femtoseconds was tricky
Registered Member #2372
Joined:
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Posts: 62
I dont see how they are measuring this in the spec sheet. Usually to measure things that are really fast for optical type systems they use some kind of autocorrelation techinque called FROG or SPYDER. How 80 fs is relavent in a 100 MHz chip is beyond me.
Registered Member #84
Joined: Thu Feb 09 2006, 01:06PM
Location: Dallas, TX
Posts: 47
Looks like the SNR at high input frequencies is determined by the jitter. So, if you want to measure a signal at 200MHz with a 135MS/s ADC and actually achieve datasheet SNR, you would need these low jitter numbers.
Registered Member #72
Joined: Thu Feb 09 2006, 08:29AM
Location: UK St. Albans
Posts: 1659
You don't measure that level directly, so much as infer it. Fortunately very few applications actually demand that level of performance, and other defects of the converter and the rest of the system limit the dynamic range.
To ascribe a figure to sampling jitter, you would use a very clean clock source, an overtone crystal if it goes to high enough frequency, and sample a very clean signal generator set to various frequencies. One component of SNR is an input frequency and amplitude - so volts/second slope - dependent ADC jitter contribution. Plot a graph of SNR versus Fin, fit the SNR model parameters, and out pops an rms jitter figure.
One of the complications is that jitter is a single figure, whereas phase noise is a spectrum. The jitter is an integral from several kHz to several MHz offset. Different processes affect noise at different offsets (1/f noise, power supply sensitivities, AWGN), so trying to engineer for low noise by using the jitter figure alone is doomed to partial success.
How do these guys get such low jitter and consequently such low phase noise?
No, they work for low phase noise within the relevant offset spectrum, so consequently low jitter. And they *won't* strive to get excellent phase noise outside those offsets unless it just happens to drop out of the process, as it doesn't affect their final jitter spec.
As an example of a very demanding application where the jitter figure is not as extreme as it first appears, the adjacent channel leakage specification for a 3G radio signal. As noise is proportional to signal amplitude, and the signal being measured has in excess of a 10dB crest factor, the RMS signal must be backed off by >10dB from full scale to avoid overloading, and now the jitter-induced noise floor is more than 10dB better than it appeared from doing the jitter sums against a full scale input signal (rms noise porportional to rms signal). Also the measurement bandwidth is around 5MHz, 10-20dB better than the Nyquist bandwidth of the converter, another leg-up on the way to approaching 80dBc for the overall measurement.
Registered Member #84
Joined: Thu Feb 09 2006, 01:06PM
Location: Dallas, TX
Posts: 47
Dr. Slack, thanks for your reply!
Dr. Slack wrote ...
To ascribe a figure to sampling jitter, you would use a very clean clock source, an overtone crystal if it goes to high enough frequency, and sample a very clean signal generator set to various frequencies. One component of SNR is an input frequency and amplitude - so volts/second slope - dependent ADC jitter contribution. Plot a graph of SNR versus Fin, fit the SNR model parameters, and out pops an rms jitter figure.
Yep. Posted a paper on the SNR fitting method one post above yours.
Dr. Slack wrote ...
One of the complications is that jitter is a single figure, whereas phase noise is a spectrum. The jitter is an integral from several kHz to several MHz offset. Different processes affect noise at different offsets (1/f noise, power supply sensitivities, AWGN), so trying to engineer for low noise by using the jitter figure alone is doomed to partial success.
So, here is a paper on the equation to get from phase noise to rms jitter. (not for you Dr. Slack. I'm quite sure you are already aware of this. )
I will simply contend that you can also imply low phase noise from rms jitter if the rms jitter is sufficiently low. If I say my source has 100fs of jitter, can you honestly say it might have bad phase noise? As the jitter gets larger, you can draw all kinds of phase noise plots to fit. I'll give you those cases, but those weren't the ones I was talking about. ADI's device states 60fs. The clock source was probably in the neighborhood of 30fs. I would say low phase noise = low jitter = low phase noise in this case.
Dr. Slack wrote ...
How do these guys get such low jitter and consequently such low phase noise?
No, they work for low phase noise within the relevant offset spectrum, so consequently low jitter. And they *won't* strive to get excellent phase noise outside those offsets unless it just happens to drop out of the process, as it doesn't affect their final jitter spec.
I think you are confused with my statement. I was talking about the device manufacturers and not the basestation manufacturers in this post. The device manufacturers would need two sources... one for the input and one for the clock. It's helpful if they are the same. Rohde-Schwarz makes a nice source in the SMA100A that has good phase noise that computes to a jitter of ~110fs at 100MHz (B22 option). Phase noise counts bigtime when you have a converter at a low sample rate (80MS/s), a high number of points (>128K), and a high SNR (80dBFS) since now you can directly measuring the input close in phase noise of the source.
Dr. Slack wrote ...
As an example of a very demanding application where the jitter figure is not as extreme as it first appears, the adjacent channel leakage specification for a 3G radio signal. As noise is proportional to signal amplitude, and the signal being measured has in excess of a 10dB crest factor, the RMS signal must be backed off by >10dB from full scale to avoid overloading, and now the jitter-induced noise floor is more than 10dB better than it appeared from doing the jitter sums against a full scale input signal (rms noise porportional to rms signal). Also the measurement bandwidth is around 5MHz, 10-20dB better than the Nyquist bandwidth of the converter, another leg-up on the way to approaching 80dBc for the overall measurement.
I get where you are coming from... backed off signal, 1st Nyquist, limited bandwidth, and low crest factor. That is all a recipe for not needing super jitter or phase noise. You must be able to get away with several hundred femtoseconds of rms jitter in this case. I see this basestation example as the special case, though. You set the experiment up where the variables are all in your favor. Nothing wrong with that.
Registered Member #30
Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706
I think like Dr. Slack said, it's the other way round. Converter and oscillator designers work for low noise, and that results in low jitter.
Note, I said low noise, not just low phase noise. Ordinary ("amplitude") noise gets converted to phase noise, which is where jitter comes from. This is sometimes called AM-to-PM conversion, and it happens in any non-linear circuit, such as an ADC's clocking circuit, which has to make some decision about when exactly the clock changed state.
The jitter measurement technique I'm familiar with involves driving the converter from high-purity clock and test signals, measuring the phase noise sidebands in a large number of averaged FFTs of the converter's digital output, and inferring the jitter from that measurement, minus the known contributions of quantization noise, converter noise and non-linearity, and the test oscillators' own noise sidebands.
If the clock and test signals were pure sine waves to start with (Dr. Slack's overtone oscillator?) and then put through high-Q passive filters to attenuate noise sidebands even further, they could have arbitrarily low jitter.
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80fs RMS Jitter - How to measure?
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