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PCB Help > Multi Minature Brick > IGBT current sharing > Eagle Layout ~:-(

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Adam Horden

Mon Apr 10 2006, 12:04PM

Registered Member #176 Joined: Tue Feb 14 2006, 09:35PM
Location:
Posts: 44

Hi All,

I am after some PCB design help.

There has been some talk on the TCBOUK list on desiging a PCB to act as a Multi Miniature Brick. This is basically 5 IGBTS in parallel with tvs accross each igbts to protect it against bad quenching etc. These MMBS will be use din OLTC and the such and have the same rating as a CM600. They are good for a total of 1kA within limits and 2kA out of limits with excessive gate driver Eg 30V.

I took the challange and decided to design these pcbs. Problem is I have hit some design snags and I little stuck on how to overcome them.

The version in the picture below is version 1.

Mmb Pcb Ver1

This is just the basic top view with no traces. 5 IGBTS 4PF50D devices with gate damping resistors and zener diode clamping.

Mmb Pcb Ver1 Bottom

The bottom trace. The gate connection cuts right into the high current laminate and I am not happy with this. I would want to have the same copper content for the top and bottom of the high current traces connecting the igbts.

Mmb Pcb Ver1 Top

The top trace gets the full copper content. I think this is going to lead to non current sharing.

So after thinking hard and decideing what to do next I looked around and found that people like the OSMC (open source motor controller) guys and some of the more high current papers I found actually have a high current pcb for conneting the IGBTS and leave the gate componets right off the pcb.

You you imagine the gate componets in the middle of the pcb you would have large cirulating currents arround the edge of the board that can interfere with the gate signal. This would happen with the design I showed above.

I decided to just use standard Molex connectors right ontop of the gate connects and leave eveything off the PCB. I can etch a small PCB for gate componets and just use twisted pair to connect everything.

Mmb Pcb Ver2 Bottom

Apart from figuring out how to take an output from the MMB I think this design is the best. The igbts over hang the pcb to be bolted to the heatsink.

Do you think leaving the gate components off the pcb is the best move and connect them with say 50mm of twisted pair to a small pcb that has the required gate components?

Does any one have an idea how to incorprate it all into a single PCB saying using two more inner layers?

Adam

ragnar

Mon Apr 10 2006, 12:06PM

Registered Member #63 Joined: Thu Feb 09 2006, 06:18AM
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Posts: 1425

Have you considered connecting the drains straight to the heatsink instead of the PCB, then connect to the heatsink?

Steve Conner

Mon Apr 10 2006, 12:15PM

Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706

Hi Adam

I would definitely use a 4 layer PCB. That board looks awfully big for only 4 IGBTs.

HV Enthusiast

Mon Apr 10 2006, 12:18PM

Registered Member #15 Joined: Thu Feb 02 2006, 01:11PM
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Posts: 3068

How are you proposing to ensure current sharing between the devices???

Adam Horden

Mon Apr 10 2006, 12:24PM

Registered Member #176 Joined: Tue Feb 14 2006, 09:35PM
Location:
Posts: 44

Steve Conner wrote ...

Hi Adam

I would definitely use a 4 layer PCB. That board looks awfully big for only 4 IGBTs.

5 IGBTS.

I decided to go with 5. This way I can keep with the adive that Richie Burnett gave me when he siad that the only way to stop devices exploding is to run them within there datasheet ratings and I have been doing this with all my oltcs.

Its not to big; bigger on the screen I think. Its about 100mm by 40mm.

Steve on a 4 layer PCB in eagle what do I use for the inner layers? I am using Golden Phonix as the board house for this.

Would you run the gates on the inner layer? and just use the bottom trace as a refrence? I know the emitters and collectors have to go on the outer layers.

I am worried that the gates are sujectable to noise due to the large currents running around the edge of the PCB and the gates would be smack in the middle of this so there is large DI DT. Unless I am wrong here.

I could make it smaller but I have 2mm clearnace and this is good to 900V.

Also with 5 Devices you could then use 1200V IGBTS.

EDIT EV:

EastVoltResearch wrote ...

How are you proposing to ensure current sharing between the devices???

Carefull layout. Identical copper runs to each device. This method has been tried and tested by my self and Derek Woodroffe using double sided copper clad PCB. I have some photos of the proto I will upload them in a mo.

Adam

Steve Conner

Mon Apr 10 2006, 12:30PM

Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706

I use layers 2 and 15 as the inner layers in Eagle. If you like, I'll check the board files and gerber files for you before you send it to Gold Phoenix. I'm planning to order my DRSSTC boards from them this weekend anyway.

On a 4 layer board I would have all 4 layers just solid sheets of copper. The 2 outer ones would be emitter and collector, and the 2 inner ones would be gate and the kelvin emitter connection for the gate drive. (I guess)

I would use the outer layers for emitter and collector because the inner layers only connect through thin plated-through holes that would probably blow with the high current. On the outer layers you can get at the copper directly, to bolt terminals or solder heavy wires to it.

Adam Horden

Mon Apr 10 2006, 12:48PM

Registered Member #176 Joined: Tue Feb 14 2006, 09:35PM
Location:
Posts: 44

EDIT:Found them. Looking in the wrong place I will finish laying it out now as there is a 2 week lead on 4 layer PCBS with golden phonix.

I do not have layers 2 and 15 in my version of Eagle?

Do I have to enable them somewhere. My layers then start at 100 but nothing hidden on 2 and 15.

I get top and bottom traces that about it.

Adam

Steve Conner

Mon Apr 10 2006, 02:41PM

Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706

I think you need to edit the script file mylayers.scr and run it in the board editor.

Adam Horden

Mon Apr 10 2006, 03:35PM

Registered Member #176 Joined: Tue Feb 14 2006, 09:35PM
Location:
Posts: 44

Steve Conner wrote ...

I think you need to edit the script file mylayers.scr and run it in the board editor.

Hi Steve,

Would you add the gate componets to the PCB or just have headers for the gates and do the rest off the PCB? I am planning to use SMDS for the gate componets to compress the size.

Adam

robert

Mon Apr 10 2006, 04:14PM

Registered Member #188 Joined: Thu Feb 16 2006, 05:18PM
Location:
Posts: 67

Maybe your EAGLE licence is limited to 2 layers only?
If so, you have to upgrade the licence to support 4 layers.

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