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MOSFET input charicteristics

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Z28Fistergod

Sun May 17 2009, 02:19AM

Registered Member #2040 Joined: Fri Mar 20 2009, 10:13PM
Location: Fairfax VA
Posts: 180

I recently got a new (to me) HP4275a LCR meter. This has multiple frequencies from 10KHz to 10MHz, internal bias to 35 volts, adjustable test signal level, simultaneous measurement of L or C or impedance and ESR or Q or phase angle, pretty much everything I could ask for.

So putting it to good use I decided to see how the gate capacitance and ESR of a large power MOSFET varies with voltage. What I found was very surprising. I knew the gate capacitance varied with applied voltage, but I never would have guessed by this much.

The MOSFET is a STW18N40, 18 Amps at 400 Volts makes it prime for your basic SSTC duty. What I did was make many measurements while varying the bias voltage from -18 to +18 volts at a typical SSTC operating frequency of 200KHz. On the graph I didn't include the results when the bias is less than -4 volts or more than +7 volts as there was very little change beyond these values.

One interesting point is the spike in ESR centered at 3.4 volts, I believe this accounts for the "step" sometimes seen in the switching transitions. Also something else is the high Q values at zero volts, below -3 volts, and above 6 volts, which makes it easy for the gate to have these parasitic resonations if we are not careful with the stray inductance. Fortunately for us the Q rapidly drops off as we approach the threshold voltage of 4 volts and this helps to keep the resonations reasonable.

Anyway check out the graph for yourself.

P.S. The graphing software I have doesn't have the ability to make multiple Y axis labels so I had to divide the ESR values by 10 and the Q values by 100 to get them to fit on the graph. So when reading from the graph multiply the values by 10 for ESR and 100 for Q. The capacitance is in nF.

Sulaiman

Sun May 17 2009, 10:18AM

Registered Member #162 Joined: Mon Feb 13 2006, 10:25AM
Location: United Kingdom
Posts: 3140

Very interresting,

could you draw or describe the test circuit
and what is meant by esr and Q in this setup?

Z28Fistergod

Sun May 17 2009, 12:33PM

Registered Member #2040 Joined: Fri Mar 20 2009, 10:13PM
Location: Fairfax VA
Posts: 180

The test circuit is very simple, the MOSFET is connected to the LCR meter. ESR stands for equivalent series resistance. Q is quality factor, it is a measure of the quality or purity of a reactive component. As you know all reactive components have some internal resistance. The Q factor is a measure of reactive impedance divided by the resistance. So a higher Q factor means the component is closer to a pure inductor or a pure capacitor.

In a series resonant circuit there is a phenomenon called resonant voltage rise, which can be calculated with the formula VCr=VQr. Where VCr is the voltage across the capacitor at resonance, V is the applied voltage and Qr is the Q of the circuit at resonance. So you can see that the the resonant voltage rise is directly related to the Q of the circuit.

So a MOSFET with a high Q is more succeptable to ringing at the switching transitions.

GeordieBoy

Sun May 17 2009, 01:27PM

Registered Member #1232 Joined: Wed Jan 16 2008, 10:53PM
Location: Doon tha Toon!
Posts: 881

As you can see MOSFETs are highly non-linear devices! The rise in your measured ESR in the region of 3 volts is likely caused by the device entering the linear region. As you said this is the region in which the "Miller effect" causes the well-known plateau in switching waveforms.

MOSFETs possess three basic capacitances:
1. Cgs which dominates the input impedance of the device in the pinch-off and saturated regions.
2. Cds which dominates the output impedance when in the pinch-off region.
3. Cdg which is nicknamed the Miller capacitance and dominates the input impedance whilst passing through the linear region.

The input impedance ESR likely rises in the region of the gate threshold voltage because this is causing the device to turn on. This then drives current through Cdg and results in dissipation in the channel of the device. This additional dissipation in the device channel is shown as an increase in ESR by your measurement instrument.

I'd assume the drain and source were not shorted together for this measurement? You will see a different input impedance characteristic if you short-circuit the drain and source together.

These swings in input impedance of the MOSFET's gate don't usually have much implication for square-wave drive applications, other than the need to supply enough current to overcome the Miller capacitance during drain voltage rise/fall.

However, in applications using resonant gate-drive like Class D / Class E RF amplifiers they must be taken into account. The input impedance of the amplifier can often change dramatically as the drive power level is varied and the MOSFET begins to switch. This can cause a situation where the gate drive circuit is out-of-tune with low drive power, and then suddenly snaps into tune as the drive power is increased. The drive power can then be decreased considerably before the amplifier "snaps off" again. This drive hysteresis is a result of the behaviour you have observed. A similar thing also occurs if the supply voltage to the drain is varied. Device capacitances change with drain voltage and modulation linearity can be wrecked in badly designed amplifiers.

-Richie,

klugesmith

Sun May 17 2009, 03:58PM

Registered Member #2099 Joined: Wed Apr 29 2009, 12:22AM
Location: Los Altos, California
Posts: 1716

That's an interesting experiment, thank you for sharing it. Do you know the magnitude of AC excitation voltage or current which is superimposed on the charted DC bias voltage?

As for the nonlinearity...
MOSFET datasheets give the value of an important parameter, Gate Charge, in nanocoulombs.

In the land of direct current, suppose you charge the gate with a small constant current, and infer its capacitance from dV/dt. When Vgs reaches threshold, the device continues to accept charge with a much slower increase in voltage. A very loose analogy would be the temperature of water heated with constant power, when it reaches the boiling point.

Sulaiman

Sun May 17 2009, 06:02PM

Registered Member #162 Joined: Mon Feb 13 2006, 10:25AM
Location: United Kingdom
Posts: 3140

I meant was there any drain bias during testing? (sorry, I should have been clearer)
I'm curious as to how the esr is measured as low when Vgs is low.
I just can't accept the drop in esr as Vgs decreases below 3v4 on your graph.
As posted above, check the ac voltage level injected during testing,
if you're plotting with 100mV increments in Vgs then the ac signal should be <<100mV pk-pk.

Can anyone explain ?

I'll have a quick test tomorrow at work and report back.
P.S. couldn't find STW18N40 on STM site or my usual databases.
P.P.S. clip a scope probe on using x10 and watch what's going on,
discovering/knowing the range of conditions over which you can trust your equipment is vital,
some of the strange waveshapes in simple non-powered circuits that have non-linear devices amaze me!
P.P.P.S The gate charge vs gate voltage graphs in datasheets are commonly produced by using 1mA constant current into the gate, so the horizontal axis is actually usec instead of nC. (nC=mA.uS)

Z28Fistergod

Mon May 18 2009, 12:46AM

Registered Member #2040 Joined: Fri Mar 20 2009, 10:13PM
Location: Fairfax VA
Posts: 180

Sulaiman, can you explain to me why the ac signal should be less than 100mv? I can understand why the signal level should be less than the successive steps in voltage, but is this the only reason? I read your post and it got me wondering so I made a few quick measurements, with a signal of 50mv RMS. I found that the point of peak ESR shifted to 4V or so, but the overall shape of the curve remained the same, with the ESR dropping below the spike

Playing around with the voltage a bit I found the measurements highly dependent on the oscillator level. So how do we determine which measurement to believe?

Sulaiman

Mon May 18 2009, 05:40PM

Registered Member #162 Joined: Mon Feb 13 2006, 10:25AM
Location: United Kingdom
Posts: 3140

Yes, the peak-to-peak amplitude of the ac signal should be much less than the dc measuring interval or the results will be 'blurred', that's all.

Since your results with 50 mVrms are similar,
I guess I just don't understand mosfets enough!

I didn't have spare time today (even lunch time)
so maybe tomorrow I'll do a quick test.

Steve Conner

Mon May 18 2009, 05:57PM

Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706

I'd want to know what the drain was connected to. Miller effect means that whatever is on the drain will influence the gate, possibly more than the characteristics of the gate itself.

Z28Fistergod

Tue May 19 2009, 12:48AM

Registered Member #2040 Joined: Fri Mar 20 2009, 10:13PM
Location: Fairfax VA
Posts: 180

The drain wasn't biased at all during that test, I plan on doing another test with the drain bias soon. Although now I'm more worried about what the correct test level is.

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