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Registered Member #205
Joined: Sat Feb 18 2006, 11:59AM
Location: Skørping, Denmark
Posts: 741
All,
I have to drive this fiber optic led from industrial fiberoptics :
The manufacturer suggests this drive scheme:
It appears to me, that the led is kept forward biased at 6.6mA constantly, with the 750 ohm resistor, and then slammed wide open with the 100ohm/18pF combo, delivering another 50mA. These 50mA must pass trough the gate of the 74ACT08
The datasheet of the 74ACT08 states, that the recommended current trough one pin is 24mA, and the maximum allowable current is 50mA. Also, a total of 100mA through VCC is allowed.
So, should I just drive the chip with one gate at it's absolute maximum, and the other 3 neutralised as advised, or would it be advisable to parallel a couple of them, thus placing the operating conditions within specifications.
Registered Member #65
Joined: Thu Feb 09 2006, 06:43AM
Location:
Posts: 1155
What is the expected on-time duty cycle and switching frequency? I suspect if you are running at 5v, than the average power dissipation for the package type is the limiting constraint. High speed logic tends to operate more quickly at higher voltages, and manufacturers chip limits can vary depending on manufacturer.
Note the signal propagation through the same chip should be closely matched, but separate current limiting resisters should still be used on both gates. However, the technique should probably be avoided for the sake of noise.
Registered Member #195
Joined: Fri Feb 17 2006, 08:27PM
Location: Berkeley, ca.
Posts: 1111
hi Finn, since you have a 7408 the other 3 gates can be paralleled just connect all the inputs and outputs and put it in series with the first gate so the first gate drives the inputs the other 3 gates. the 3 gates should act like buffers. the only drawback to this course of action is that the package may heat up and this will get worse with frequency. you also might use a mosfet driver. what is your application
Registered Member #162
Joined: Mon Feb 13 2006, 10:25AM
Location: United Kingdom
Posts: 3141
manufacturers rarely give a suggested circuit that makes their product look bad
the AC(T) outputs typically are (Vcc - 0v7) high and (gnd + 0v4) low
the 'on' voltage of the led is c2v
when the ACT o/p is low, the 100R will pull down the 750R to c1v ... led off
when the ACT o/p is high then (5v -2v)/750 + (4v3 - 2v)/100 = 4 + 23 = 27 mA led current 23mA is nicely in-spec.
the note about putting bypass caps next to the power pin is really important
I have used three 74ACT240 gates with paralleled inputs and one 150R resistor per output to drive 50 Ohm cable successfully so paralleling outputs is ok but one resistor per output is what I'd recommend.
Registered Member #205
Joined: Sat Feb 18 2006, 11:59AM
Location: Skørping, Denmark
Posts: 741
Thank you all for the answers, Sulaiman in particular for a comprehensive one.
It turns out, there is an application bulletin that describes the parallelling of gates which Teravolt describes:
I will parallel the gates in this fasion, then.
The application is to transfer a pwm signal from an Arduino Due to a fiber led. The pwm frequency probably 50kHz, 8Bit resolution, for ~20Mbps signal. This PWM signla will be smoothed out with a lowpass filter, and describe a ramp to serve as voltage reference in a nice buck konverter.....
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Is it safe/useful/advisable to parallel logic gates?
