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It is with you to improve: - Make the global reset line to start register values - Add OCD input (shutdown or cycle-skip) - Add start-burst square generator
Registered Member #2292
Joined: Fri Aug 14 2009, 05:33PM
Location: The Wild West AKA Arizona
Posts: 795
Gregory,
Looks good. I did a ADPLL a little while back in a Xilinx FPGA and my largest issue was jitter from the loop filter being set wrong.
Take special care to tune the loop filter, if the filter isn't set right it can lead to major instability in phase regulation, I noved a small amount of jitter in your video, indicating you many need to tweak your filter a little more.
Registered Member #2922
Joined: Sun Jun 13 2010, 12:08AM
Location:
Posts: 226
Thanks.
The jitter you saw is only 10ns and is caused by temporal quantization noise by the FPGA 10ns (100Mhz) sampling rate. To get rid of that jitter only increasing the FPGA clock.
I think the loop is very estable. Can you test it in your FPGA driver? I still don't have a driver to test it.
Registered Member #2292
Joined: Fri Aug 14 2009, 05:33PM
Location: The Wild West AKA Arizona
Posts: 795
Gregory wrote ...
Thanks.
The jitter you saw is only 10ns and is caused by temporal quantization noise by the FPGA 10ns (100Mhz) sampling rate. To get rid of that jitter only increasing the FPGA clock.
I think the loop is very estable. Can you test it in your FPGA driver? I still don't have a driver to test it.
If you don't have a drive then how did you get those output waveforms on the scope?
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Digital VHDL ADPLL for time-lead generation
