Digital VHDL ADPLL for time-lead generation
Gregory, Wed Dec 10 2014, 03:15AMHello guys, I just implemented a digital ramp-up time-lead generator for digital drivers.
- Recursive moving-average with configurable order.
- Input synchronizer for feedback signal.
- Configurable time-lead.
- Source Code
- Simulation print-screen
- Youtube video of implemented code
It is with you to improve:
- Make the global reset line to start register values
- Add OCD input (shutdown or cycle-skip)
- Add start-burst square generator
Re: Digital VHDL ADPLL for time-lead generation
Goodchild, Wed Dec 10 2014, 05:22AM
Gregory,
Looks good. I did a ADPLL a little while back in a Xilinx FPGA and my largest issue was jitter from the loop filter being set wrong.
Take special care to tune the loop filter, if the filter isn't set right it can lead to major instability in phase regulation, I noved a small amount of jitter in your video, indicating you many need to tweak your filter a little more.
Keep up the great work.
Goodchild, Wed Dec 10 2014, 05:22AM
Gregory,
Looks good. I did a ADPLL a little while back in a Xilinx FPGA and my largest issue was jitter from the loop filter being set wrong.
Take special care to tune the loop filter, if the filter isn't set right it can lead to major instability in phase regulation, I noved a small amount of jitter in your video, indicating you many need to tweak your filter a little more.
Keep up the great work.
Re: Digital VHDL ADPLL for time-lead generation
Gregory, Wed Dec 10 2014, 03:31PM
Thanks.
The jitter you saw is only 10ns and is caused by temporal quantization noise by the FPGA 10ns (100Mhz) sampling rate. To get rid of that jitter only increasing the FPGA clock.
I think the loop is very estable. Can you test it in your FPGA driver? I still don't have a driver to test it.
Gregory, Wed Dec 10 2014, 03:31PM
Thanks.
The jitter you saw is only 10ns and is caused by temporal quantization noise by the FPGA 10ns (100Mhz) sampling rate. To get rid of that jitter only increasing the FPGA clock.
I think the loop is very estable. Can you test it in your FPGA driver? I still don't have a driver to test it.
Re: Digital VHDL ADPLL for time-lead generation
Goodchild, Thu Dec 11 2014, 07:12AM
If you don't have a drive then how did you get those output waveforms on the scope?
Goodchild, Thu Dec 11 2014, 07:12AM
Gregory wrote ...
Thanks.
The jitter you saw is only 10ns and is caused by temporal quantization noise by the FPGA 10ns (100Mhz) sampling rate. To get rid of that jitter only increasing the FPGA clock.
I think the loop is very estable. Can you test it in your FPGA driver? I still don't have a driver to test it.
Thanks.
The jitter you saw is only 10ns and is caused by temporal quantization noise by the FPGA 10ns (100Mhz) sampling rate. To get rid of that jitter only increasing the FPGA clock.
I think the loop is very estable. Can you test it in your FPGA driver? I still don't have a driver to test it.
If you don't have a drive then how did you get those output waveforms on the scope?
Re: Digital VHDL ADPLL for time-lead generation
Gregory, Thu Dec 11 2014, 07:13AM
On a nexys 4 development board. Not a coil FPGA driver.
Gregory, Thu Dec 11 2014, 07:13AM
On a nexys 4 development board. Not a coil FPGA driver.
Re: Digital VHDL ADPLL for time-lead generation
Goodchild, Fri Dec 12 2014, 02:14PM
Ah ok.
When I get some more time I may give your code a try, it looks well written.
Goodchild, Fri Dec 12 2014, 02:14PM
Ah ok.
When I get some more time I may give your code a try, it looks well written.
Print this page