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Registered Member #2288
Joined: Wed Aug 12 2009, 10:42PM
Location: Cambridge, MA
Posts: 179
I'm working on a digital project that needs a clock fanout, and I have a fundamental confusion about the current rating of these chips. Take for instance this one:
The test conditions terminate outputs to 50 ohm loads, there are 9 outputs, and VCC=3.3v, and the maximum core and driver current draw of the entire chip "Total Device Current with Loads on all outputs" is 95mA, and the per channel output current for 'high' output is 7mA.
But, 3.3v/50ohm * 9 outputs = 594mA. Even if we say clocks are 50% duty cycle, that's still 297mA. And the per channel output current of high should be 3.3/50=66mA, but the chip is only rated to 7mA out!
So how does this work? It seems as though their test condition and recommended termination would blow up the chip...
Sure, I could series terminate, but I don't want to for this application because I need fast rise and low jitter, and the datasheet seems to say that parallel termination is fine: "Test conditions are: Ftest = 100 MHz, Load = 5 pF in parallel with 50 Ω"
Edit: forgot to point out, this is just one example, but almost all models and manufacturers seem to have this same paradox in the datasheets
Registered Member #65
Joined: Thu Feb 09 2006, 06:43AM
Location:
Posts: 1155
LVDS shared line intro:
The impedance of the differential lines is critical, and thus the termination may vary by a large degree between PCBs...
Most LVDS transceiver chips and FPGAs have extensive documentation on how to chain high speed device clock lines. This is not a simple matter in the upper spectrum, and if you have PLL clock multipliers in each chip it may prove difficult to compensate for clock drifts.
It would seem that LVDS is a constant current loop in normal use, so the voltages on the lines are in the 100's of mv range. Accordingly the current into a 50 O)hm resistor math does not apply. That said, I can't make head nor tail of the 'voltage swing' charts which are supposed to be 50Ohm terminated.
Looking back I can't see all the stones and I'm wondering if I stepped on a turtle.
On the bright side I think I've figured it out properly. The datasheet is muddy when it comes to termination in each circumstance. The current numbers and voltage swings are not maximum ratings, they are typical ratings for a capacitive load without 50 Ohm termination.
Registered Member #72
Joined: Thu Feb 09 2006, 08:29AM
Location: UK St. Albans
Posts: 1659
dude_500 wrote ...
This isn't LVDS, it's a CMOS single ended output chip.
Yes, and LVCMOS isn't intended to be terminated in 50ohms. The 50 ohms termination referred to in the data sheet is, I think, the clock input termination.
This chip is designed so that it can be used with 50 Ohm termination. The power use is specified with a capacitive termination because this gives the lowest power numbers. The timings are specified with 50 Ohm because this gives the lowest timing numbers (and it's compatible with the kind of equipment you'd measure picosecond timing with).
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Clock Fanout Current Rating
