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Registered Member #1960
Joined: Thu Feb 05 2009, 11:57PM
Location:
Posts: 48
Hello. I'm looking at driving a N-MOSFET for load connect/disconnect (as a relay). This is going into a battery monitoring system.
I'm looking at a NMOS inverter as a possible solution. I want the application to be "no power usage in idle", the NMOS inverter is "no power usage in active".
I want to control the gate with a 3V3 signal, so a PMOS inverter is out of the question. Gate voltage out is ~ 9V to 13V.
I know I can use additional discretes to make this circuit do what I want it to, but I want to keep the total parts count to a minimum. If there is an easy way to do this, please help me out :)
Registered Member #3900
Joined: Thu May 19 2011, 08:28PM
Location:
Posts: 600
yes, the picture you have linked is a logic inverter(or buffer with a swap of devices). In order to use the mosfet as a load switch it has to be in series with it. Then when the mosfet is active the load is active.
Registered Member #1960
Joined: Thu Feb 05 2009, 11:57PM
Location:
Posts: 48
Billybobjoe wrote ...
What are you trying to switch on/off? For most loads, you can just replace the resistor in your diagram with your load.
I'm trying to switch on/off a "huge" N-MOSFET, this is a safety disconnect from too deep discharge - for the battery.
Ben Solon wrote ...
yes, the picture you have linked is a logic inverter(or buffer with a swap of devices). In order to use the mosfet as a load switch it has to be in series with it. Then when the mosfet is active the load is active.
The load is not resistive, it is a MOSFET gate. This load is capacitive, and active high. This is fine. But I'm looking to replace the logic inverter with something - so that power consumption during "cutoff" is nonexistent.
I can do this with some extra npn's and resistors, to make the PMOS inverter work - but is there a more elegant solution?
Registered Member #72
Joined: Thu Feb 09 2006, 08:29AM
Location: UK St. Albans
Posts: 1659
Why are you using an NMOS inverter? A CMOS inverter would be 'no power either active or inactive'.
If you're using NMOS because you have to, then increasing the value of the pullup resistor will decrease your power consumption, at the cost of taking longer to charge the gate capacitance.
Registered Member #1960
Joined: Thu Feb 05 2009, 11:57PM
Location:
Posts: 48
My 3V3 levels isn't enough for CMOS logic. Additional components are needed.
I'm open to different implementations, as I definitely see the shortcomings of the NMOS inverter. Currently tho; the NMOS is the only one that can give a relatively high voltage out, for a small control voltage in.
Registered Member #152
Joined: Sun Feb 12 2006, 03:36PM
Location: Czech Rep.
Posts: 3384
What about two transistors, NPN and PNP, cascaded in common emitter configuration? The PNP will have a pull down resistor on its output. If the input will be 0 volts, the output will be 0 volts as well, with zero current draw (well maybe some microamps of leakage current)
Registered Member #1960
Joined: Thu Feb 05 2009, 11:57PM
Location:
Posts: 48
Dr. Dark Current wrote ...
What about two transistors, NPN and PNP, cascaded in common emitter configuration? The PNP will have a pull down resistor on its output. If the input will be 0 volts, the output will be 0 volts as well, with zero current draw (well maybe some microamps of leakage current)
I think you've solved my problems. This seems to do exactly what I want to do. To make sure we are on the same page: A bipolar totem pole MOSFET driver is suitable for this application.
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