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Registered Member #65
Joined: Thu Feb 09 2006, 06:43AM
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Posts: 1155
The latching of the DDS configuration (page 3) is synced to the main clock to avoid output instability:
Given multiple chips have unique multiplier settling times, one cannot guarantee these will be in-phase if the clock multipliers are active. If I use the 30Mhz clocked DDS mode will truly phase matched concurrent signals be possible in the mixer, and avoid having to fix it with the DDS chips built-in limited "proprietary angle rotation algorithm"?
Registered Member #29
Joined: Fri Feb 03 2006, 09:00AM
Location: Hasselt, Belgium
Posts: 500
You should be able to synchronize following the procedure described in the data sheet. The DDS uses an internal integer-N PLL to generate a 180MHz clock. As with all Integer-N PLL multipliers, there should be no phase ambiguity between the reference clock and the local oscillator. (sigma-delta fractional frequency interpolators used in fractional N PLLs can exhibit phase ambiguity).
I have never used this chip, so I cannot say for sure how it will work, but I have used other chips (AD9858) that required PLL frequency multiplication. Generating 1GHz for this chip from a 10 MHz clock using an integer-N PLL posed no synchronization problems. Be careful to keep delays in DDS clock lines and any phase accumulator reset lines equal, or you will need to compensate using the DDS phase adjustment.
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Quirks in syncing multiple DDS RF sources for mixer
