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The goals of the following design is: 1) Minimum part count 2) Maximum efficiency over all operating voltage range (including ~0V range) to eliminate heatsinking requirements 3) No-cap-in-load detection and circuit protection 4) Automatic shut-off when cap repolarization detected (major recuperational gauss design and induction coilgun issue)
Here is the first version of the proposed circuit:
The following cycling operation is assumed: 1) Initially there is no current flowing through Rctrl, so In pin of left driver is 0 and Out pin goes high, opening the K1 MOSFET. 2) Current building up in the transformer while Cf cap is discharged through Rf. 3) After some time Cf discharged down to the LOW threshold level of the Enable pin of the left driver, forcing it's Out to go LOW, switching off the K1 in result. 4) When MOSFET closes, voltage over the primary and secondary of the transformer inverts and current starts to flow through Dhv to the output cap. It also runs through Rctrl chain, so voltage on the In pin of the left driver is over HIGH threshold which forces it's output to be LOW. 5) While K1 is closed, Cf is charged up to the voltage level, clamped by DZ1. This level is assumed to be just a little over the HIGH threshold of the Enable pin of the left driver (3-4V for most drivers). Cf reaches it's up bound very fast, so driver gets enabled pretty soon. But it can't go HIGH until it's In will fall down to LOW threshold level. And this will not happen until the current in the secondary will deplete to the minimum level determined by Rctrl chain resistance and LOW threshold level of the In pin of the left driver. As a result, K1 is not getting open again until transformer is ready for another portion of the input current. This way short-circuiting of the output becomes a normal operation mode for this voltage converter.
As a result, the time transformer is sucking current from the supply is always constant and independent from the input or output voltage (input voltage is assumed to be const). But the second part of the cycle, when trans drains to the load, has a variable timing which controlled by the output current - first cycle is not started again until the current depletes to the certain level. This current-controlled timing lets achieve almost the same efficiency level over all output voltage range. Average output current is close to const resulting in a constant speed of cap voltage rise speed over the whole range of voltage.
The right driver and K2 are the major protection elements. During a shot of an induction coilgun or recuperational gauss gun (those use non-polar caps) caps' voltage is inverted. When it happens, current through Rctrl chain increases greatly as cap starts to discharge through the secondary of the trans and output diode. If load is not disconnected fast, the secondary and Dhv will burn. The overcurrent case is sensed by Rctrl chain. If voltage on Ra rises to the HIGH threshold of the right driver, it switches it's Out to LOW, forcing K2 to close disconnecting the Cload. Together with K2 the Enable pin of the right driver goes LOW, latching the driver in a LOW output state even when it's In goes LOW again as a result of current stop running through Rctrl. The system is halted up untill Cpause is charged back to the HIGH threshold of Enable pin through built-in pullup resistor (all MOSFET drivers with Enable have those). When it happens, right driver opens again. If Cload is still inverted, latch happens again. System will try to reboot until the Cload will return to the proper polarity.
If Cload is not connected at all, then on the second cycle voltage of the K1' drain will jump high to the level clamped by DZ2+DZ3+0.6V of D2. If it will happen, the current through Rctrl will be very high and right driver will sense it the same way as inverted polarity of the Cload, halting the converter the same way.
Output voltage control circuit I used to is a chain of zener diodes and optocoupler.
New version. Still not tested, just based on previous practical experience, calculations and datasheets:
Notes:
Time constant of the part of the cycle when transformer sucks the current from supply is determined by R1 and Cf. It is approximately equal to 2*R*C seconds (if Cf is 330pF then trans will charge for ~20us). The second part of cycle, when Q1 is off and current flows through secondary into load lasts until the output current falls to the certain level. This relaxation time depends on the output voltage at the moment - the higher it is, the faster the transformer empties it's stored energy. The new current build-up cycle starts when voltage at In2 falls below LOW input level which is around 1.3V for the IC used in schematic. F.e. if you want the new cycle to start when output current falls down to 100mA, then use R2+R3=13Ohm. Assume you decided the protection current to be 10A. If so, then R3 is 0.15Ohm and R2 is 12.85Ohm.
The DZ3 and DZ4 zeners are for protection only. Those should not pay a part in normal operation. Only in error conditions the current flows through them. The DZ1 activates the protection sequence in case output cap is not connected. It's zener voltage should be picked in accordance to the Q1 maximum drain voltage: Vz(DZ1) = Vd(Q1)-Vz(DZ3)-Vz(DZ4)-Vf(D1) Volts. If maximum drain-source voltage of Q1 is 50V, then using 43V as DZ1 should do the work.
The repetitive reverse voltage rating of output rectifier, D2, should be two times higher than output voltage the charger is designed for. For 400V cap charger the 800V diode should be used. Pay attention to the surge current rating - diode must be able to sustain without damage the overcurrenting (10A in the example above) for 10us at least.
D4 is the diode with low-leakage current rating and reverse voltage rating at least equal to the output voltage the charger is designed for. DZv is a chain of zener diodes. The sum of their's zener voltages determine the shut-down output voltage level. F.e. for 400V charger two 200V zeners may be used. Use ones with minimum power rating to minimize the leakage current. One TVS instead of chain of zeners will not work due to low precision and high leakage.
Q2 is the main protection element of the charger. If any error condition determined (no load, over-currenting, output voltage level reached) it is closed by driver1 effectively disconnecting the charger from the load. The drain-source voltage of Q1 must be at least equal to the output voltage the charger is designed for (double rating will be better). Q1 must be able to sustain surge current during overcurrenting without damage (10A in the example above). Choose the one with low on-resistance rating as most of the time this MOSFET stays in ON state and it is not switched frequently.
D3 and D5 are low-voltage (20V) pulse diodes (~2A at surge) with preferably low leakage current (<1uA below 6V).
C3 is a filter cap and must have lowest ESR possible (think about ceramic caps) and be connected as close as possible to the IC' Vcc and Gnd pins. C1 is an electrolithic cap with high ripple-current rating (at least equal to the peak current in the primary at the end of current-suck cycle). It's "+" must be as close as possible to the trans' primary and "-" is close to the source-pin of Q1 to minimize the parasitic inductance and resistance in a Q1-C1-Tprim loop.
Registered Member #2906
Joined: Sun Jun 06 2010, 02:20AM
Location: Dresden, Germany
Posts: 727
blablabla i dont like the design, the schematic is cryptic, and.. well hiere was once a lot of more text. i deleted it the design could work, but there is no benefit over ordering a free sample of the LT3750 and build the stuff the easy way. should be much cheaper too.
edit2: my edit and your following text came up at the same time. f.... edit3: thanks for your added description. helps a lot.
That is what I'm planning to try to build after all:
Output current-controlled flyback voltage converter for capacitors charging. Actively-protected from the following error conditions: 1) No capacitor in load connected; 2) Load capacitor repolarized; *Short circuit at output is considered to be normal operating condition.
Preset numbers:
[IPrimPeak] Amperes is a peak value of current flowing into primary winding of the transformer during the feed cycle when current is building up;
[ISecPeak] and [ISecMin] Amperes is a maximum and minimum values of the current, respectively, flowing from secondary winding of the transformer into load during the output cycle;
[IProtect] Amperes is a current flowing through secondary during the error conditions for a short period of time (~10us);
[VOut] Volts is an output voltage the converter is designed for;
Parts:
R2 and R3 are current-controlling resistors with 3:1 resistance ratio (NOT wire-wound - metal-oxide or carbon, with minimum parasitic inductance). Their sum resistance (R2+R3) is determined by the [ISecMin] value: R2+R3 = ( 1.3 / [ISecMin] ) Ohm; [IProtect] can be calculated then as (1.3 / R3) A or simply 4*[ISecMin]. Keep in mind that [ISecPeak] must be less than [IProtect] and is recommended to be {2...3}*[ISecMin].
D1: 20V, [IPrimPeak] A surge current rated;
D2: 2*[VOut] V, fast switching diode, [IProtect] A surge current rated, [ISecPeak] A repetitive pulse current;
D3: 20V, low-leakage, low forward voltage drop diode, [IProtect] A surge current rated;
D4: [VOut] V, general purpose diode with low leakage current;
D5: 20V, low-leakage, 3A surge current rated;
D6: 20V, [IProtect] A surge current rated, preferably low parasitic capacitance at Vr=12V;
Q1: minimum 40V drain-source voltage; DZ1: 12V less than Vds of Q1 (DZ1=28V for 40V MOSFET), [IPrimPeak] A surge current rated;
Q2: [VOut] V, [IProtect] A surge current rated MOSFET with preferably low Rds rather than low Qg;
DZv is a chain of low-power zener diodes with low leakage current, connected in series for performing a voltage-control function; total zener voltage of the chain should be a couple volts lower than [VOut] V.
Cf is a cap controlling the duration of the feed cycle (when Q1 is open and transformer sucks current from supply through the primary winding). This time constant is roughly equal to (1.5*Cf*R1) seconds. To choose Cf precisely, put a resistor in place of primary transformer winding and using the oscilloscope check the time the resistor holds 12V voltage drop on it. To double this value, use double capacity cap and so on. Keep in mind that feed cycle starts with transformer not completely deenergized as switching performed at [ISecMin] A, not at 0 A (so derate saturation time).
Notes:
The effective turns ratio of the transfomer is recommended to be 12:(0.5*[VOut]). This way the average duration of the output cycle over the whole output voltage range will be equal to the constant duration of the feed cycle.
Lower output current, predetermined functionality. I mean, designing the charger with UC3842 comes to designing the charger based on that IC. But I needed to made a charger with some unusual functionality, so I made a circuit based on simple elements, and MOSFET driver I used is an industry-standard device with simple functionality, MCP14E9 is 3A peak, MCP14E3 is 4A peak, MCP14E6 is 2A, and there are plenty of other drivers all of the same kind. If all functionality my charger has can be achieved with smg like UC3842 with lower external elements count - well, this would be even better. But I can not design a multifunctional_IC-based charger without having that IC physically tested first (I had an unexpected glithes even with 556 timers) as datasheets are always missing smg and for multifunction IC those pages are always undescriptive. What are the propagation delays, for example? How can I implement a protection logic with undeterminable reaction time on hazardous conditions? MOSFET drivers are simple to implement in a new design and those are all fully-specified and fast. Anyway, I have parts coming soon, will see how my device will work.
Registered Member #1565
Joined: Wed Jun 25 2008, 09:08PM
Location: Norway
Posts: 159
UC3842: No cap voltage: limit voltage on comp-pin.
No cap protection: use some smaller capacitor on a seperate winding to detect too big peaks and drive the comp-pin low (disables the IC)
Polarity reversal: There is no switch in the route (coil & diode only), but limiting the comp-voltage should limit the PWM to safe values. or drive comp low (1 cycle or less?) Given it's not isolated, a direct sense should be doable.
The chip got built-in FET-driver, and can in some cases regulate it's own voltage from external supply.
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