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Registered Member #3900
Joined: Thu May 19 2011, 08:28PM
Location:
Posts: 600
hey all, I have been doing a lot of work with logic lately, and I have a question that nobody seems to answer. how does edge triggered logic work? looking at it from the non logic pov, I can see two ways to do this, but they are both just ways of converting a rising or falling edge to a brief level logic pulse. using just logic gates, how can I make a logic system edge triggered? if this is not possible, what is an easy way to use analog circuits to help the digital along?
Registered Member #30
Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706
The essence of edge triggered logic is flip-flops, whose clock inputs are edge triggered.
You have to be careful with the concept. If you somehow made an entire logic circuit edge triggered (which would be a struggle, because Boolean algebra deals with levels, not transitions) then you would find that it was unreliable and extra sensitive to noise.
I think the concept that comes closest to what you want is synchronous logic. As well as the usual gates, you use flip-flops, all clocked by the same master clock. Most complicated logic systems are designed this way.
The big advantage is that the flip-flops act as memories, so you can build state machines: things whose outputs depend on past inputs as well as current ones. A microprocessor, indeed a Turing machine, is just a glorified state machine. Indeed, microprocessors are built with synchronous logic, and that's why they need a clock to work.
Getting back to your "just logic gates" requirement, I'd start by making flip-flops with edge triggered clock inputs out of the gates. Any good digital electronics textbook should show how.
Registered Member #72
Joined: Thu Feb 09 2006, 08:29AM
Location: UK St. Albans
Posts: 1659
Download the data sheet for a 74HC74, and look at the diagram in there for how the edge triggered latch works. Don't look at a TTL version, they do clever things with multi-emitter transistors which obfuscates the logic.
Hint, it's two level gated latches, one tracking for clock high, the other tracking for clock low. Think around the timing hazard, and how it's overcome.
Registered Member #3900
Joined: Thu May 19 2011, 08:28PM
Location:
Posts: 600
Ok, thanks, I think it makes sense now. My aim is to fully understand the flip flops used in drsstc's. Once I finish my drsstc, I am going to be designing my own logic circuit for it. I fully understand every part of all of Steve's logic boards minus the flip flops. I understand the function, just not the equivalent circuit. Anyways, thanks for the quick tips.
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edge triggered logic
