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LT3750 Capacitor Charger

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RussT

Tue Nov 08 2011, 10:20PM

Registered Member #4190 Joined: Sat Nov 05 2011, 09:47PM
Location: BC, Canada
Posts: 5

Is there anyone on the forum that can help me with my LT3750 application?
I have the LT3750 working, but barely. I will wait for responses before posting more info.
Thanks!!
Russ

Steve Maurer

Wed Nov 09 2011, 03:22AM

Registered Member #133 Joined: Fri Feb 10 2006, 10:27PM
Location: Pensacola, Florida
Posts: 47

I'm familiar with the LT3750. Describe your configuration and what you are encountering and I'll try to help.

- Steve

RussT

Wed Nov 09 2011, 09:10PM

Registered Member #4190 Joined: Sat Nov 05 2011, 09:47PM
Location: BC, Canada
Posts: 5

Thanks Steve. I got the part to work but seem to have trouble with the sense resistors and the current setting. I think I might have a poorly laid out pcb contributing to the issue. Please see attached JPG. Also, I have attached a pcb of another member's version of laying out the LT4750. I must admit, his looks far "cleaner" than mine.

See the file pcb_layout for a PDF view of the pcb.

I used jumpers to try to set the charging currents. However, after research on-line I got the idea that the jumpers may be causing parasitic inductance. I removed the jumpers and shorted out the jumper positions directly. Success!! I immediately got charging on the cap.

However, a couple of things. I have now got 2 x 0.016 ohm resistors in parallel as well as another 0.026 ohm resistor also in parallel. This finally got me average currents (as seem on the input Vtrans line) of about 3 AMPS. That seems a very low total sense resistance. The datasheet calls for 0.012 ohms for a 6 AMP charger (page 13 on datasheet). So, my first question is why am I having to use such a low sense resistor value?

Secondly, I am using the PHT6NQ10T NMOS. With the 3 AMP current draw and after about 1/2 hours continuous operation I just fried the PHT6NQ10T.

My goal is to use a 5 AMP 12VDC laptop power supply. I wish to charge with the highest current that will not overload either the power supply or the NMOS.

So, maybe I am not sizing the NMOS properly.

Parameters are:

Input: 12VDC
Output: 375 VDC
Charging Capacitor: 600uF

Many questions. Hope this helps.
Cheers,
Russ :)

1320872985 4190 FT127972 1275966098 2843 Ft86875 Capacitorcharger

]pcb_layout.pdf[/file]

Steve Maurer

Thu Nov 10 2011, 02:35AM

Registered Member #133 Joined: Fri Feb 10 2006, 10:27PM
Location: Pensacola, Florida
Posts: 47

Hi Russ,

Some layout changes will definitely help, as PWB layout is critical with the LT3750 and the LT3751. Some attention to design details is necessary with these chips, and a good design requires careful planning.

Here are a few tips:

You need to remove copper pour away from the RVout and RDCM resistors (pins 9 and 8 respectively) and also away from the traces that lead from these resistors back to the LT3750. The RVout and RDCM signals are quite susceptible to noise. Take a look at the data sheet for the LT3751, as it depicts a good sample layout that will help keep noise away from these signals.

A snubber may be required across the primary winding of the flyback transformer in order to prevent overvoltage of the PHT6NQ10T (Vds rated at 100 V). Again, the LT3751 data sheet has some good information on how to protect the MOSFET with a snubber circuit (if needed). You may also consider using additional copper pour for the MOSFET drain if you need to pull more heat away from the part. Youâ€™ll have to perform some thermal calculations to determine if this is necessary.

Provided you keep Vds and the thermals within the part ratings, the PHT6NQ10T should work, as the gate charge is fairly low (21 nC).

Try to use a layout similar to the LT3751 sample layout in Linear Techâ€™s LT3751 data sheet. The LT3751 has some additional bells and whistles (and thus extra pins), but the sample data sheet layout will help you visualize what needs to be done to reduce noise on the PWB.

You may be getting noise on the charge enable pin input, as its trace is currently running parallel to the trace that feeds the three current sense resistors. I would move this trace and also reduce the number of required current sense resistors to a minimum.

Utilize separate ground planes for your primary and secondary sides of the transformer and tie them together at just one point.

Working with these controllers can be a challenge, but will yield a reliable, compact design once the details are worked out.

Regards,

Steve

RussT

Thu Nov 10 2011, 06:42PM

Registered Member #4190 Joined: Sat Nov 05 2011, 09:47PM
Location: BC, Canada
Posts: 5

Thanks so much Steve for your excellent suggestions.

1. Just curious, what do you think of the small pcb layout? If I follow a similar layout, maybe this would yeild a good design? Or do you see issues with it?

2. Please see attached a snipet from a document I found on enhancing the LT3750. The author has added an R*C snubber, gate drive resistor and a 75 ohm resistor to the source pin with some caps in parallel. Do you think these might be useful? I would disregard the circuitry to the right of M1 as this serves to capture losses due to drain voltage spikes. I will need to have a low-noise switcher as the final product will require CE certification for low EMI/EMR output. L2 in the diagram might reduce parasitic noise??

3. LT's datasheet calls for 2 x 56uF/25V caps in parallel on the Vtrans line to the TX. I will be powering the unit from a 12VDC/5AMP laptop power supply. Do I need these caps? Or can I use say a large 1000uF/25V radial electrolytic (through-hole) instead? I have plenty of room on the pcb.

4. I am also going to try using this FET: Digikey# IPD110N12N3 GCT-ND

It has 120V rating, and 11 mOhm Rds On. That should be very good at heat dissipation. Good choice?

Thanks Steve!
Russ

]lt3750_enhancements.pdf[/file]

Steve Maurer

Fri Nov 11 2011, 04:24AM

Registered Member #133 Joined: Fri Feb 10 2006, 10:27PM
Location: Pensacola, Florida
Posts: 47

The bottom .jpg layout is definitely better. At a quick glance, it appears that most of the necessary design criteria were met with this layout. I would have used two capacitors on Vtrans though (read second to last paragraph below).

I always include a gate resistor in my power supply designs. It offers a means of slowing down the leading edge if needed (helps reduce emissions). You can always place a zero Ohm jumper in its place if you do not need it. Make sure not to make the gate resistor too large or you will heat up the MOSFET due to an excessively slow turn on. I also usually provide a placeholder on the PWB for a fast diode that is placed in parallel with the gate resistor (anode facing the gate) in order to provide a fast gate charge bleed off during MOSFET turn off. If your gate resistor is really small, then you may not need the reverse gate diode.

Use the snubber, especially if there is potential for MOSFET Vds overvoltage breakdown. Using a snubber will sometimes permit you to use lower voltage MOSFETs which will have better switching characteristics.

As far as snubber topology, I like to use RCD snubbers, as you can reduce losses. However, an RC snubber may also be used and can be effective at protecting the MOSFET. If you are designing for low cost, then use the RC (lower parts count). If you want efficiency, then use the RCD.

The following article discusses the differences between RC and RCD snubbers for flyback transformers: http://www.maxim-ic.com/app-notes/index.mvp/id/848

Flyback transformers are emissions noisy by the nature of their operation. If you need to pass CE emissions, then in addition to a careful layout, I would also suggest placing filter components at your supply input. I generally use a common mode choke followed by an X-capacitor (line-to-line), Y-capacitors to chassis ground, and differential chokes. All of this gets placed prior to your input. If you can get by with slower output capacitor charging times, then you can reduce your input switch current, lower the emissions and also permit the use of much smaller magnetics components for the filter network.

Traces to the Vtrans capacitors and the snubber components need to be as short as possible to reduce loop current areas, which will reduce emissions.

L2 was likely placed in the simulation schematic in order to represent the leakage inductance of the flyback.

The purpose of having two 56 uF capacitors on the Vtrans line (instead of a single capacitor) is to reduce ESR. I would use multiple capacitors.

The gate charge for the IPD110N12N3 is not quite as good as the PHT6NQ10T, but it is still reasonable. Keep in mind that the MOSFET conduction times are quite short and that Rds_on may not be as important of a parameter in this design as Vds, Qg, and Id. You might be better off with a FQB19N20L if you desire higher Vds and more current capability (Vds=200 V, Id=21 A).

Regards,

Steve

RussT

Fri Nov 11 2011, 08:46PM

Registered Member #4190 Joined: Sat Nov 05 2011, 09:47PM
Location: BC, Canada
Posts: 5

Hi Steve,
Thanks a ton...your info is really valuable and interesting!

1. Referring to the PDF on the enhancements, the author has also placed a 75 ohm resistor to the SOURCE, and parallaled this with a 5nF cap and a 1uF cap. Do you see any value in this for my app? Is it for noise reduction?

I have just placed the IPD110N12N3 FET on my proto pcb. There was an immediate reduction in losses as the input current dropped 500mA (from 4.5A to 4 A) without any change in charge rate. It is charging the 600uF cap to 350VDC in less than 2 sec. That is very impressive.

Also, with the low Rsd ON of 11m ohms, the FET only now gets midly warm to the touch. Again awesome!

The Coilcraft TX (DA2034-AL) does run very hot at about 60*C. However, Coilcraft says this is well within parameters.

Russ

Steve Maurer

Sat Nov 12 2011, 03:16PM

Registered Member #133 Joined: Fri Feb 10 2006, 10:27PM
Location: Pensacola, Florida
Posts: 47

The 75 Ohm resistor, and associated capacitors being used with the current sense input can filter the current sense signal to compensate for parasitic capacitances (Vgs and Vds) and parasitic inductance (Isense resistor). These parasitics should be kept as low as feasible by careful selection of the MOSFET, current sense resistor, and trace lengths on the PWB. The parasitics may be reduced by choosing a MOSFET with low capacitances and using a low inductance style current sense resistor.

Magnetics components are generally ok with temperature rises up to 40 C above ambient. This limits the core temperature below 125 C even at a high ambient temperature of 85 C. Important things to consider are core temperature and wire temperature. Keeping the core temperature low is important, as core permeability usually drops significantly above 125 C (depends on the core material). As the permeability drops, magnetics components lose their inductance and begin to act like a resistor.

If the PHT6NQ10T MOSFET was running hot, then the Rds_on will be higher than what was stated on the data sheet. Rds_on increases when the junction temperature rises. This is why you can get â€œthermal runawayâ€ with a MOSFET.

Based on packaging, Theta_ja and Theta_jc will likely be lower with the IPD110N12N3 than the PHT6NQ10T, which will also keep the IPD110N12N3 MOSFET cooler.

Regards,

Steve

RussT

Sat Nov 12 2011, 03:39PM

Registered Member #4190 Joined: Sat Nov 05 2011, 09:47PM
Location: BC, Canada
Posts: 5

Starting to make much sense Steve. Thanks.
Question: The LT3750 is a rather pricey IC compared to say a UC3843 PWM Controller. Just wondering abut the differences between these IC's in my application? Cost is a factor. I am currently using the UC3843 but I found it difficult to raise the peak current as the FET got extremely HOT compared to the FET using the LT3750. That is one reason I wanted to try out the LT3750.

With my current design, the transformer whines near the end of the charge. And, if I lower the sense resistors to boost current, the TX whines so loud I cannot use it in a product. The LT3750 seems to do things better.

However, maybe it is I do not know what I am doing well enough to get the UC3843 to work as I hoped.

Attached is schematic showing the setup for the UC3843.

Russ

Steve Maurer

Mon Nov 14 2011, 11:37AM

Registered Member #133 Joined: Fri Feb 10 2006, 10:27PM
Location: Pensacola, Florida
Posts: 47

Remember that flyback transformers store energy in the core during the input current pulse and discharge this stored energy when the input pulse shuts off. The magnitude of the stored energy is based on the duty cycle (which determines the length of time that the current will build) and the primary inductance of the transformer. The duty cycle needs to be optimized for the design in order to permit maximum energy transfer and keep the flyback core from saturating.

Based on the RT value used, the UC3843 may be running at too high of a duty cycle. Check to make sure that the UC3843 is running within the recommended frequency range of the transformer and that the transformer is permitted enough time to discharge the energy that has been stored during the input current pulse.

Regards,

Steve

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