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Registered Member #2063
Joined: Sat Apr 04 2009, 03:16PM
Location: Toronto
Posts: 352
ture table are easy, you have inputs on the left and output on the right heres a truth table for an "and" gate and "or" gate colum A and B are inputs and colum X is output. in TTL logic, 5 volts is a 1, and 0 volts is a 0
Registered Member #2431
Joined: Tue Oct 13 2009, 09:47PM
Location: Chico, CA. USA
Posts: 5639
Grenadier wrote ...
Then you use a Karnaugh Map.
Also, sig too long :p
Yes, your sig is too damn long and yes for the K-map point Grenadier makes. Im more than twice your age, therefore i remember what the dinosaurs were like. (Wholly crap--Im older than dirt)
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Logic Gates
