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Joined: Tue Oct 16 2007, 02:01AM
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Relating to my other post about PCB design, I am restarting. For this PCB, I will be using a 512 BGA proccessor (XMOS G4), and 8 high speed ADC's (AD9212), plus a bunch of amplification as they are reading photodiode currents. This needs to stay small, so I will be using double sided component mounting. I would like opinions on setting up this PCB well to avoid changing anything in the middle and suffering the consequences. A quick signal description: Generic processor stuff doesn't need special attention in regards to EM interference. The main issue lies in the routing of amplification stages before the ADC's, and the output of the ADC's are high speed differential lines (there will be a decoder before the processor).
Here is what I am thinking in terms of a stackup: One power plane will have 1 volt, and the other 3.3v as both are dominant. There will be some 5v routing inter spruced in the 3v3 layer. The 1v layer will actually be cut into two sections, one for digital and one for analog (primarily for the ADC's). I plan on having through vias, and blind vias from signal 1-2, and signal 4-3.
Any thoughts?
EDIT: Now I am thinking that via layout is not good. Any thoughts on how I should arrange the blind vias? I could go buried vias if needed.
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Designing a DRC for a 8 layer PCB
