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Registered Member #1062
Joined: Tue Oct 16 2007, 02:01AM
Location:
Posts: 1529
I am having trouble routing these last signals on an XMOS board. The idea is to have a xmos module that can plug into base boards, like the gumstix. I primarily did this so I can have parallax strips with different sensor spacings, but it could easily be used for anything else. There are 2 SMD connectors on the bottom, one for JTAG and one for an 8 bit port, plus 4 1 bit ports. If someone could take a look at it, that would be great! Feel free to play with spacing and such.
I would like to keep it at 2 layers with 15mill vias (6/6 traces), as cost will be half! ]final_plan.zip[/file]
Registered Member #1062
Joined: Tue Oct 16 2007, 02:01AM
Location:
Posts: 1529
This is my first attempt at hand routing, so I expected trouble.
That looks great! Could you upload the eagle files?
EDIT: Looked at your changes, that will help in the future! Via's you added look too small (min hole size is .015"). Can you elaborate on the tidying up? I thought I did a pretty good job on the whole left side :)
Registered Member #1667
Joined: Sat Aug 30 2008, 09:57PM
Location:
Posts: 374
>> I would like to keep it at 2 layers with 15mill vias yes, I saw that in the DRC but after an hour of routing I thought "what the ... am I doing right now?" and let it be. You can always sacrafice a bit of the restring in favour of a larger drill if it has to be. Mask alignment errors are not very likely to destroy the via at that point because the drill holes are filled.
Registered Member #30
Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706
Isn't .015" just the default minimum hole size in Eagle's DRC?
You have to ask the PCB manufacturer you're going to use what their actual minimum hole size is. Eagle doesn't know that, its defaults lead to boards that are pretty agricultural by today's standards.
Registered Member #1062
Joined: Tue Oct 16 2007, 02:01AM
Location:
Posts: 1529
I have been working on this, and got them all routed with 15 mill vias except for 3 traces. I also was able to clean up lots of the traces and get rid of some vias, and managed to make the board quite a bit smaller as a product of the cleaning. I also think I got rid of the 6 mill traces (unless i missed some). there is still 6 mill spacing, but considering the chip leads themselves dont pass a 8mill DRC, I am fine with that.
If you can, could you take a look at the last three traces?
Thanks a bunch! ]final_plan.zip[/file]
EDIT: nvm, it says 5 airwires, though I can only see 4. I bet I left a tiny one somewhere... I can fix the ground airwire connection to the center pad easily by moving the 2 pin header, I am mainly concerned about the 3 signal wires right now.
Registered Member #30
Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706
To find those mysterious airwires, just turn off all the layers except "Dimension" and "Unrouted", they will be obvious.
Eagle's track placing algorithm is a little random, sometimes tracks don't quite connect to a pad and a minuscule airwire is left. Especially if you place imperial components on a metric grid or vice versa.
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Trouble routing a PCB
