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High order filters

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GeordieBoy

Tue Mar 16 2010, 09:03PM

Registered Member #1232 Joined: Wed Jan 16 2008, 10:53PM
Location: Doon tha Toon!
Posts: 881

> When people want to filter a DC waveform that moves from one value to another...

Perhaps therein lies the problem! DC that moves from one level to another by definition contains more spectral energy than just DC content. It also contains high frequency AC content as well which must be passed by the lowpass filter. (Dr Slack I realise that you already knew this! but mentioned it here for the benefit of others.)

A simple technique that can be used to minimse the ripple from PWM reconstruction is two use two PWM modules running at the same frequency but in anti-phase. You filter both of them seperately with simple RC filters then sum their outputs.

If you think of two PWM waveforms at 50% duty ratio, one starting out high and the other starting out low. Then filter them both. You get two DC signals of 0.5 each with a little bit of triangular shaped ripple. The neat thing is that the two ripple waveforms are complementary triangle waveforms that cancel out when added together. The ripple cancellation is theoretically perfect when the duty ratio is 0.5 but is still worthwhile for other ratios.

Another relatively simple analogue option to eliminate the undesirable ripple that is frequency modulating your VCO is this. Use an I/O line for the PWM that can be tri-stated. Take this line high to charge the filter capacitor when you want to increase the VCO operating frequency, take it low when you want to discharge the cap and lower the frequency. When the frequency is spot on, you tri-state the I/O line (make it a high-impedance input) and this will leave whatever level of charge is on the filter capacitor without incurring ripple from a PWM pulse train. (The PLL's used for FM radio local oscillators use this type of 3-level comparator to eliminate modulation sidebands from the RF output. The 3-level comparator leaves the VCO frequency alone as long as it is doing the right thing! Hence no ripple!)

> I have maxed out my pwm frequency at 4khz. This give me adequate resolution to vary the duty, which will control my voltage to a PLL's VCO. This is for a control-loop.

I'm not sure why you need the VCO to be quite so agile, but if you really want lightening fast response to changes in frequency without any lag or overshoot you might want to look at DDS chips like Analog Device's AD9834.

For those who have not come across these DDS chips before, they are a frequency synthesiser on a chip. They are a self contained digital system that calculates the required output waveform at whatever frequency you tell it to. A typical design running from a 24MHz system clock can generate any frequency from DC to about 8MHz with a programming resolution of maybe 0.1Hz. Because they are a digital system they can be controlled over SPI easily from any microcontroller. They would fit right into your digital control system and eliminate the analogue interface part that seems to be giving you headaches.

I hope this has given you a few ideas,

-Richie,

Dr. Slack

Wed Mar 17 2010, 05:43AM

Registered Member #72 Joined: Thu Feb 09 2006, 08:29AM
Location: UK St. Albans
Posts: 1659

I found this active analog chip based on your suggestion, Neil.

Uhh? I didn't make any suggestion, at least not about choosing specific Butterworth hardware.

As a general rule, to optimise the time*bandwidth product, keep the order low, no more than 3rd order. If you want to improve the ripple that gets through from your PWM, then if the ripple is at constant frequency, which should be easy to arrange if you code a constant period PWM, then add a stopband zero to notch out the fundamental PWM freqeuncy. These introduce very little delay into your passband. I feel (engineer's seat of pants here) that used in a control loop, modest overshoot will not be a problem, which is why I'm not going to suggest a Bessel, but something steeper.

So what I would suggest is ...

Design a 3rd order elliptic, play around with the bandwidth parameter until the stopband zero occurs at 4kHz, then simulate it to see what response you've got. The filter design program will ask you for other parameters, like passband ripple and stopband ripple. The former gets traded off against delay, try 1dB to start with. The latter controls how much the other harmonics of the PWM will be attenuated, the ones which aren't killed by being hit by the stopband zero. Only you know how much suppression is needed. Again, suppression gets traded off against delay, try 40dB (you'll struggle to see 1% ripple on a 'scope) to start with.

Just for the experience, see if you can find a high order Bessel design, then simulate it in the time domain. I found it quite freaky when I first did this, that after putting a step into it, nothing happened at the output for a while, then it went woooooomph to the final value without a tremor, just the way that other filters don't.

BTW, I've had this sig line for a few weeks now, but it may suit your application perfectly. With sufficient mucking about, a PWM through a filter into a VCO might do something like what you want, but it might be more appropriate to take a plane, or walk the pig, by using a real DAC to tune the VCO, or digits to drive a DDS, or even (assuming the VCO in question is the back end of a 4046, by generating a low frequency from your uC and multiplying it up with the PLL chip). If you don't have the funds for these more appropriate solutions, then flinging the pig through a filter may be the only option.

Thanks Richie, "DC that moves about" was written quite provocatively

Steve Conner

Wed Mar 17 2010, 10:10AM

Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706

I'm going to stick my neck out and guess that Iamsmooth is using an Arduino, and doesn't know how to write a driver for a DAC or DDS, so he's stuck with the PWM module.

Douglas Self did a study to see what kind of filter was best for DC offset protection in audio power amps. The task of this filter is to reject loud bass notes, but trigger the protection as quickly as possible on the application of DC.

He usd Spice to study bass rejection vs. triggering delay, with a single RC, dual cascaded RC, and a Bessel active filter. His method was to design the three filters for the required amount of attenuation at 20Hz, so that full power would only just fail to trigger the detector. Then he measured the triggering delay on a step input.

He found that the single RC worked best, then the cascaded one, with the Bessel in third place.

In the context of this application, make of that what you will...

Dr. Slack

Wed Mar 17 2010, 12:02PM

Registered Member #72 Joined: Thu Feb 09 2006, 08:29AM
Location: UK St. Albans
Posts: 1659

He found that the single RC worked best, then the cascaded one, with the Bessel in third place ...

... for the particular undocumented ratios (hence filter stopband rejection) between the 20Hz tolerate level, the DC tolerate level and the post-filter trip point. So results not easily transferred, nor strictly applying to Mr Smooth's problem.

But an interesting result nonetheless.

Perhaps the most important lessons of the *one reply based on actual measurement* on this thread are that

a) It's not intuitively obvious what filter is going to perform best in any application
b) It's difficult to specify the behaviour you want in the real real, and convert that directly to "filter like" specifications
b) high order is not necessarily the way to go

Mattski

Wed Mar 17 2010, 10:04PM

Registered Member #1792 Joined: Fri Oct 31 2008, 08:12PM
Location: University of California
Posts: 527

I happened to be looking at

There's some good resources attached to some posts including a master's thesis that you may find useful as a partial overview of filter design.

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