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Registered Member #30
Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706
A way to do it with low leakage inductance is:
Wind a 1:1:1:1:1 with a bundle of 5 wires all twisted together
Series up two pairs of windings to get a 1:(1+1):(1+1) = 1:2:2
For still lower leakage inductance you can take a piece of Cat5 ethernet cable (8 cores) and wind it round a ferrite toroid. Identify the 4 twisted pairs of wires. One wire in each pair is a primary, and you parallel them up, to get 4 parallel primaries. The remaining four wires are secondaries and you can series two pairs of them to get a 1:2:2.
If you're going to such lengths to minimize leakage inductance, then all of the leads going from the transformer to the gate driver and FETs must be in tightly twisted pairs too.
Registered Member #2315
Joined: Tue Aug 25 2009, 02:35AM
Location: Leyte, PH
Posts: 161
Hi Steve, Dan, 10111
thanks for the informative bits!
I finally managed to make one... 10primary (210uH) , 20T sec (around 800uH) x 2 with a leakage inductance of about 0.40uH.. I think its OK enough ...though I made it on a SMALLish TV flyback UU core..ferrite torroids (>1" OD)are VERY hard to come by...
some pics...
primary winding "bundled" whites..
here is my core .. but it DOES work
the secondaries
its on my 2nd (soon to be DR) SSTC... secondary running on 218KHz with topload...
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