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Registered Member #190
Joined: Fri Feb 17 2006, 12:00AM
Location:
Posts: 1567
Neil,
Is it your design that has been implemented in the PLL chips these days?
I'm not that familiar with PID design. WOuld a simple integrator using an opamp like the MC3403 work, followed by a unity amp with a gain of -1 to correct the sign of the integrator? If so, does this mean I need a negative rail voltage for the opamp to work properly?
Registered Member #1232
Joined: Wed Jan 16 2008, 10:53PM
Location: Doon tha Toon!
Posts: 881
IamSmooth. there's loads of useful information about PLL's here:
There are also links there that take you to pages that will explain things like PID control loop design and compensation for stability.
It is impossible to say whether a "simple integrator" would "work" without knowing what you are trying to achieve, along with the gain of the VCO, phase detector gain etc, then calculating loop gain, and analysing gain margin and phase margin.
A PLL is just like any other CONTROL SYSTEM, in that it tries its best to make "something" track a reference or "demand" signal. That "something" could be VCO frequency or VCO phase, and it might track it perfectly, or track it with an error, or probably track it with some time-lag and maybe even overshoot and ringing. Before you embark on designing a PLL it helps to have these things quantified then you can work out the maths to get to where you want to be.
I'm not going to try to explain control theory as it is a massive subject that gets mathematical very quickly and there are many textbooks about the subject. But, in a nutshell a low gain around the loop gives poor slugish tracking of changes in the reference and a bad steady-state error, (ie it probably won't get quite where you want it to get to,) but it definitely won't go unstable and burst into oscillation. Conversely, a high loop gain gives a faster response to changes and a lower steady-state error, but it is more likely to overshoot or ring if you get the design wrong, or break into complete instability if you get it really wrong. A control engineers job is to make the output of the system get to where it is meant to be as quickly as possible, with no overshoot and ringing, and with the minimum residual error.
Registered Member #72
Joined: Thu Feb 09 2006, 08:29AM
Location: UK St. Albans
Posts: 1659
Is the application to trigger the next switching cycle of an induction heater / SSTC?
If so, then surely an adjustable delay from the last zero crossing is going to be far simpler and more stable and easier to adjust than a PLL, which has all sorts of extra nasties waiting to snare the inexperienced. But a delay won't be self-starting, so it would need something extra to kick it any time it stopped. A 4 state PSD would be about the worst thing to use for this application, needing as it does a whole extra cycle of phase to move between acquistion and lock.
Registered Member #190
Joined: Fri Feb 17 2006, 12:00AM
Location:
Posts: 1567
Dr. Slack wrote ...
Is the application to trigger the next switching cycle of an induction heater / SSTC?
This is for an induction heater. I already have an inverter running off of a PWM chip that I can adjust with a POT. I have also made on a breadboard a PLL that I can adjust the phase with a POT by adjusting the VCOin voltage. I am looking for a simple means that it will lock onto quadrature without my having to adjust anything. Maybe a simple way does not exist.
I tried putting a simple integrator followed by a gain of -1 from the PCA1out pin to the VCOin. I found it would almost get 90 shift when I dialed up from below Fo; it would lock onto half the frequency if I came from above Fo.
I know I mentioned that the phase varied with the reference signal frequency. I have not seen what would happen if I feed the tank capacitor voltage, which has the same frequency, back in as the reference signal. With both frequencies automatically being equal, I wonder what will be the final phase shift.
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Help with HEF4046 PLL chip
