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Help with HEF4046 PLL chip

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IamSmooth

Sat Nov 28 2009, 07:13AM

Registered Member #190 Joined: Fri Feb 17 2006, 12:00AM
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I have been playing with the PLL chip to understand its functionality. I used values close to 100k and 50k for R2 and R1. C1 is 680pf. The loop filter is 100k and 10000pf. The system is running at 15v.

I input a square wave signal to the chip and bring the frequency down until it captures near 90khz. Coming from below it captures near 65khz. The lock range is larger than the capture range.

I watch the VCOout signal and notice that when it captures the frequency gets locked to my input signal. Now I thought the phase should also be held constant at 90deg off. What I see is that the phase shift gets closer or further from 90 as I vary the input signal around the middle frequency. I probed the VCOin pin and the voltage is 7.5v when the shift is 90. However, as I vary the input signal, VCOin changes, and the phase shift varies.

I thought the frequency and phase get locked. Am I missing something?

Dr. Slack

Sat Nov 28 2009, 08:36AM

Registered Member #72 Joined: Thu Feb 09 2006, 08:29AM
Location: UK St. Albans
Posts: 1659

If the phase shift varies as the locked frequency varies, then you are using a type 1 loop. This is without an integrator, and the VCO voltage is just gain*phase_shift. As gain is finite, so phase_shift must vary as VCO voltage varies.

In a type 2 loop, an integrator is included, so that at DC, the gain is inifinite (well, to all intents and purposes) so any VCO input voltage can be generated with the same phase shift at the PSD.

Type 2 is the default choice for most PLL applications, however there are some cases where the simpler dynamics of a type 1 loop make them preferable to type 2. If you want absolutely constant phase shift for turning your devices on at the right time, then type 2 is mandated.

You need to ask the question, what loop bandwidth do I want in my application? This will dictate the gain you need. You may find that that your type 1 has so much gain, that the phase shift is constant enough for your application.

If you don't have an application in mind, then it can be a bit difficult to understand all of the possibilities offered by just playing with a PLL, because there are so many variables. Different problems will lead to different solutions. Loop type, loop order, loop bandwidth, PSD type are all parameters for which the wrong choice can make or break an application.

To put it a slightly different way, if you play with a PLL until you find a configuration that "works", it may not be appropriate for the first problem you actually try to apply it to, with off-putting results. Start with the demands of a specific application, then beat on the PLL until it delivers. But be prepared to use a different configuration for the next problem.

IamSmooth

Sat Nov 28 2009, 03:57PM

Registered Member #190 Joined: Fri Feb 17 2006, 12:00AM
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Neil, when you mention a Type 2 loop you aren't referring to using PC1 or PC2 comparator pins (2 or 13)? You are referring to the loop filter? So I need to change my simple low-pass filter to an active integrator, right?

Steve Conner

Sat Nov 28 2009, 04:04PM

Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
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I found this confusing at first in the 4046 datasheet.

If you use PC1 according to the datasheet instructions, you get a Type 1 loop.

If you use PC2 according to the instructions, you get a Type 2 loop. PC2's charge dispensing circuitry makes it function as an integrator. (But it doesn't have quite as much noise rejection as a real analog integrator would.)

This is why they're called 1 and 2.

GeordieBoy

Sat Nov 28 2009, 04:12PM

Registered Member #1232 Joined: Wed Jan 16 2008, 10:53PM
Location: Doon tha Toon!
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PC1 if the standard EXOR gate (or balanced mixer thing) ?

...and PC2 is the 3-state thingy where it charges the cap if the VCO frequency is too low, leaves it alone if the frequency is spot on, and discharges it if the frequency is too high?

Is that right?

I know that the 3-state type of phase comparator is the one often used in the field of radio for PLL tuned local oscillators etc. Otherwise the 50:50 duty ratio of the EXOR phase comparator's output would always cause ripple at say 1kHz in the control voltage. The residual ripple in the VCO voltage after filtering causes unwanted sidebands in the PLL output.

-Richie,

IamSmooth

Sat Nov 28 2009, 04:16PM

Registered Member #190 Joined: Fri Feb 17 2006, 12:00AM
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So if I want to maintain exactly a 90 phase difference between the reference signal and the VCOin signal I need a type I. Type II will eliminate phase difference. Do I have this part right?

With a type I if the signal is locked, the phase is locked. If the phase on the reference signal varies (frequency fixed), VCOout will vary to maintain the phase. Right?

uzzors2k

Sat Nov 28 2009, 07:05PM

Registered Member #95 Joined: Thu Feb 09 2006, 04:57PM
Location: Norway
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GeordieBoy wrote ...

PC1 if the standard EXOR gate (or balanced mixer thing) ?

...and PC2 is the 3-state thingy where it charges the cap if the VCO frequency is too low, leaves it alone if the frequency is spot on, and discharges it if the frequency is too high?

Is that right?

That's been my impression too.

Mr. Smooth like you observed in your experiment, the phase difference will vary with the input frequency's position, relative to the center frequency of the VCO. This is something I've suspected for a long time, but that somehow wasn't a problem in my PC1 PLL induction heater. What's worse is it's been built by several people now, and nobody has complained about the phase not locking properly! I don't know if we've all been lucky with the selection of VCO range or what. Recently I tried upgrading my induction heater with a new tank circuit running at 200kHz. Acquiring phase feedback signals has been tricky, and getting the thing to lock by itself hasn't worked so far...

IamSmooth wrote ...

So if I want to maintain exactly a 90 phase difference between the reference signal and the VCOin signal I need a type I. Type II will eliminate phase difference. Do I have this part right?

Yes and no. All you can guarantee is that PC1 gives a phase difference other than 0 degrees. You can trick PC2 by introducing your own phase shift in the feedback signal, thus getting an adjustable phase shift. Steve Ward did it in one of his drivers, which seems to be unpublished... Anyway, it used a Schmidt trigger and an RC low pass filter in the reference signal path. Simple and clever. I played with it a bit myself and it seems to work alright, though getting a whole 90 degrees of phase shift might require more effort. When using PC1 you can adjust the VCO range so the phase shift is exactly where you want it to be at a given frequency .

So to answer your question, there are degrees of truth here, no absolutes. Both can give you a 90 degree shift, but not by default.

GeordieBoy

Sat Nov 28 2009, 07:26PM

Registered Member #1232 Joined: Wed Jan 16 2008, 10:53PM
Location: Doon tha Toon!
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Uzzors, phase comparator type-1 locks the VCO with a nominal shift of 90 degrees between the VCO output and the reference. This is exactly 90 degrees at the centre of the VCO range, and deviates as you move towards the edges of the locking range. So if you design your PLL so that it operates comfortably within it's locking range the phase shift should be close to 90 degrees.

For precise locking in quadrature (i.e. the VCO locks at exactly 90 degrees to the reference) there is a trick using bi-stable dividers: You basically make a quadrature oscillator that produces two outputs (90 degrees apart) at the wanted frequency. This is achieved by running the VCO at a multiple of the required output frequency and then using CMOS frequency dividers to give you two outputs at the wanted frequency with 90 degrees phase difference between them. You then use one output for the PLL feedback and the other as your wanted signal. This allows you to force the wanted output to lock at +90 or -90 degrees. I think this is the trick that Steve Conner used in one of his PLL designs.

-Richie,

IamSmooth

Sat Nov 28 2009, 10:34PM

Registered Member #190 Joined: Fri Feb 17 2006, 12:00AM
Location:
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Uzzors wrote ...

Recently I tried upgrading my induction heater with a new tank circuit running at 200kHz. Acquiring phase feedback signals has been tricky, and getting the thing to lock by itself hasn't worked so far...

One of the things I did to clean up my signals is I added a ferrite bead to the gate drive right under the chip. I also shielded the gate drive lead with copper tubing and grouned it. This eliminated every bit of noise and now my waveform is absolutely perfect.

I am trying to lock onto a 90degree shift for my induction heater inverter. I want my reference signal to be exactly 90 off from my VCOout signal. I can force the issue my adding a POT to VCOin and setting the voltage to Vcc/2. I have heard that an integrator opamp can do this so I don't have to tune it manually. Is this so? Would the opamp need a negative supply voltage, or would a single supply opamp work?

As another approach, couldn't I use the Type II comparator and use the zero phase shift to match inverter voltage with current?

Dr. Slack

Sun Nov 29 2009, 07:39AM

Registered Member #72 Joined: Thu Feb 09 2006, 08:29AM
Location: UK St. Albans
Posts: 1659

The most reliable way to get quadrature is to use an EXOR as the phase detector, then put a type 2 loop behind it. Unfortunately, this may require using components additional to the 4046. Also unfortunately, an EXOR is only a phase detector, not a phase-frequency detector, so will only capture into lock once the frequency is within a loop bandwidth of where it should be. A huge advantage of the Exor or a mixer phase detector in this type of application is that it is tolerant to noise pulses, just the way a sequential logic PSD is not.

A 4 state detector will provide you both quadrature in lock and pull-in from any frequency offset. If you want to see the details of how to build a 4 state comparator, then check out

, and yes, that is the same Neil Thomas.

I wonder if a PLL is the right way to think for a TC. I would have thought that a "scope timebase" model would be better, that free-runs in the absence of a trigger, but syncs to the trigger after a delay when it's present.

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