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Registered Member #1334
Joined: Tue Feb 19 2008, 04:37PM
Location: Nr. London, UK
Posts: 615
SSTCs can run between, lets say, 100kHz and 400kHz approx.
That's between 2.5 & 10uS per cycle.
For a smallish SSTC/DRSSTC, what would a good "on" time be for the gate drivers? For a smallish FET like the IRFP450 driven from a GDT with plenty of primary "umph", what do you think the smallest pulse width you would be safe with would be.,.. At lower frequencies, would a longer on-time be advisable?
Registered Member #1232
Joined: Wed Jan 16 2008, 10:53PM
Location: Doon tha Toon!
Posts: 881
The "allowable" pulse width depends on many things:
1. GDT bandwidth 2. Gate capacitance 3. Operating frequency 4. Power dissipation in the MOSFET die 5. Desired spark appearance
etc, etc...
You need to be more specific. For a CW SSTC the on time for each MOSFET is usually just less than 50% of the total period. That way each MOSFET is on for just less than half the time and there is some deadtime in between.
Registered Member #1334
Joined: Tue Feb 19 2008, 04:37PM
Location: Nr. London, UK
Posts: 615
I'm using either a FERROXCUBE TN23/14/7-3E25 or p/n 5978006401 (type 78). These are wound with 10 turns CAT5 or similar - I haven't got the complete circuits to hand for on-line use, but its not rocket-science - great care has been taken to minimise impedance & stray capacitance in the bridge layout. Drivers are UCC3732xP.
I specified the operating frequencies & FETs above - Qg is typically 75nC from the datasheet with a max of 90nC.
Sparks? Yes please. Bigger, more varied, the better. I like both CW & pulsed!
I realise how bridges work, the reason for the original question is to tap people's practical experience as I'm introducing dead-time into the driver, and there are a raft of ways of doing that, one of the simplist being to use a monostable. If I do that and the period is fixed, a handle on the range to use would be good.
Registered Member #1232
Joined: Wed Jan 16 2008, 10:53PM
Location: Doon tha Toon!
Posts: 881
Okay. You only need to introduce enough dead-time to prevent overlap of the MOSFET's conduction times. This is essential to prevent shoot-through - A potential cause of excessive ringing and MOSFET deaths.
Increasing the deadtime further reduces output power by allowing the resonant load current to free-wheel in the fast-recovery diodes instead of being powered from the DC bus. It is also worth bearing in mind that the longer the longer the current is conducted by the free-wheel diodes during the deadtime, the higher the resulting dissipation will be in these diodes.
Typically 200ns will be sufficient deadtime for MOSFETs switching around 200kHz. At higher frequencies deadtime can be reduced with great attention paid to symmetrical drive, or a single-ended arrangement can be used to rule out cross-conduction. Conversely some large IGBT's have a long current-tail event at the end of their turn-off phase and may easily require 1us or more of deadtime.
If you are experimenting with this stuff I would build in a means to increase the deadtime up to say 20% of the total period. That way you can easily see the effect on an oscilloscope and check it is working correctly. It will also allow you to do some research yourself into what actually happens in an H-bridge dring a TC during the deadtime. You might actually be surprised how complex the behaviour can be!
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GDT pulse times in SSTCs...
