 Pulse Current Limiting With The SG3525A
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Dr. Dark Current
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Registered Member #152
Joined: Sun Feb 12 2006, 03:36PM
Location: Czech Rep.
Posts: 3384
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Ok.
Another "special feature" of this chip is that the frequency shifts some ~5% when the pulse width approaches maximum. I haven't found a way around this...
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GeordieBoy
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Registered Member #1232
Joined: Wed Jan 16 2008, 10:53PM
Location: Doon tha Toon!
Posts: 881
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Check that power supply rails, Vref, and whatever is controlling the duty ratio are all well decoupled. Sometimes little spikes from the fast switching PWM outputs coupled back to either the reference or duty ratio control input can cause things like:
1. Frequency pulling
2. Jumps in otherwise smoothly varying duty ratio
3. Mismatched duty ratios between complementary outputs in push-pull controllers.
Some of the early Unitrode controllers were notorious for this sort of thing. Their outputs slewed much faster than any previous SMPSU controllers and required RF type PCB layout practices to be used!
Also remember that these IC's are designed for SMPSU use - A small frequency shift with duty ratio is not really of significance in these applications. If you need the operating frequency to be rock-solid, then you would be better using a fixed oscillator to clock the sync input on a suitably equipped PWM controller. Syncing of multiple controllers is often done in complex SMPSUs so that all controllers in one product operate at exactly the same switching frequency. It reduces RF interference, eliminates beating and can also reduce current ripple through DC storage capacitors.
-Richie,
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