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Registered Member #989
Joined: Sat Sept 08 2007, 02:15AM
Location: São Paulo, Brazil
Posts: 476
As I know the pin 2 and 6 of the 555 must be wired together to work in that mode. the center tap of the bridge are wired direct with the center tap of the caps (the primary coil is shorted), the led is in "reverse" position :P
The GDT is 1:1:1? If not, put back-to-back 15V zeners on the gates. The GDT cap must be a little higher than 100nF, I have experienced a few problems with only 100nF, use three or four 100nF caps in parallel or a 470nF one.
Hmm, I hope I didnt forgot anything. I dont like to correct other people schematic, but that is what you asking isnt it? :P
(Someone with higher experience correct me if I am wrong on something)
Registered Member #195
Joined: Fri Feb 17 2006, 08:27PM
Location: Berkeley, ca.
Posts: 1111
if you use a d-type flipflop you can enshure that your fets won't turn on at the wrong time. disconect the 555s pin 3 from the ucc37322,1 pin3 and connect it to the D input. Connect the junction that connects at the cd40106pin4 to the clock. And finaly reconnect boath pin 3's of the ucc's to the Q out put
what should happen is the the gating will be syncronised with input train
Registered Member #33
Joined: Sat Feb 04 2006, 01:31PM
Location: Norway
Posts: 971
I have not seen anyone use turn-off synchronization in conventional SSTCs before.
Are you going to have the interrupter on the same board as the rest of the electronics? In that case, why not make it out of a gate from the 40106 instead of using a 555?
This is just an opinion, but I prefer running SSTCs from halfwave rectified mains, not interrupted, as they tend to allow a lot higher coupling without flashover, and therefore longer sparks from a given coil, in addition to the sparks looking more interesting and less of the screeching sound that interrupted SSTCs make.
Registered Member #989
Joined: Sat Sept 08 2007, 02:15AM
Location: São Paulo, Brazil
Posts: 476
I never had any problems with unsyncronized interrupter on SSTC's, because even if the mosfets turn off on half of the cycle, the current doest get the peak rate of the mosfet, so I *think* it maybe not a problem. As I said, I never had any problems with that.
Banned on 3/17/2009. Registered Member #487
Joined: Sun Jul 09 2006, 01:22AM
Location:
Posts: 617
You could eliminate the zeners and shottkys on the secondary base input. Interrupted sstc's are only screechy if you run them at a high frequency with a low duty cycle. I use 10uF on my GDT primary.
Registered Member #989
Joined: Sat Sept 08 2007, 02:15AM
Location: São Paulo, Brazil
Posts: 476
Yeah, biggest GDT cap as possible, I used 1uF for a fullbridge of IGBTs (that have higher gate capacitance than that IRFP260) and worked fine. So choose what you can find =D
Registered Member #540
Joined: Mon Feb 19 2007, 07:49PM
Location: MIT
Posts: 969
I would bias the input of the NOT gate with some resistors (pin one in your case). I have seen 10k used for bias resistors so I would think that they would be fine.
Registered Member #1157
Joined: Thu Dec 06 2007, 12:11PM
Location: Houston, TX
Posts: 307
Myke wrote ...
I would bias the input of the NOT gate with some resistors (pin one in your case). I have seen 10k used for bias resistors so I would think that they would be fine.
Why would I need to bias the input? There is already a resistor on the input of the not gate. Does it need to sink that much current?
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