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5V Data Input on a 3.3V Chip

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MRacerxdl

Sat Feb 28 2009, 04:05PM

Registered Member #989 Joined: Sat Sept 08 2007, 02:15AM
Location: SÃ£o Paulo, Brazil
Posts: 476

Hey all, I will interface a memory to my fpga, and I Have one problem.
The FPGA is only 3.3V (not 5V tolerant), and the DRAM works only with 5V.
What can I do to interface it? A 1k resistor in series and a 1n4148 to +3.3V will work?

Thanks :D

3l3ctrici7y

Sat Feb 28 2009, 07:23PM

Registered Member #1806 Joined: Sun Nov 09 2008, 04:58AM
Location: USA
Posts: 136

Something like this perhaps?

1k
+5v ---/\/\/---+--------- +3.3v part.
               |
            \  |
             -----
               ^  \   Zener
              / \     3.6v
             -----
               |
               |
              GND

Dr. Slack

Sat Feb 28 2009, 08:20PM

Registered Member #72 Joined: Thu Feb 09 2006, 08:29AM
Location: UK St. Albans
Posts: 1659

You may not have to do anything. Many 5v parts have TTL compatible I/O. The RAM may run from 5v, but what is the I/O specified at? It's unlikely to be 5v CMOS levels, I'll wager that it's low <0.8v, high >2.4v, so can be hooked up directly to a 3.3v CMOS I/O.

If you really do have to make a 5v CMOS parlay with 3.3v CMOS, then there are several ways to do it, speed and cost will determine which you choose. If you are not trying to run close to the maximum speed of either part, and only have to go 5v -> 3.3v, then you might get away with a resistor and diode clamp. But it sure won't increase the volts the other way round. For that you'll need some sort of buffer made for the job.

MRacerxdl

Sun Mar 01 2009, 05:04AM

Registered Member #989 Joined: Sat Sept 08 2007, 02:15AM
Location: SÃ£o Paulo, Brazil
Posts: 476

Hmm, 3l3ctrici7y, zeners are much slow for that use, so it wont work good.

The output of the RAM will go to a FPGA that doesnt have 5V Tolerant I/O. So it might be dangerous running it direct to the fpga. But the RAM inputs consider Logic Level 1 after 2.4V so 3.3V is 1.

That is only for a prototype, I was thinking about getting a converter TTL->LVTTL but I didnt found anything.

...

Sun Mar 01 2009, 05:52AM

Registered Member #56 Joined: Thu Feb 09 2006, 05:02AM
Location: Southern Califorina, USA
Posts: 2445

What clock frequiency are you running at? You can calculate if a resistive divider will work by looking at the current the pins can source to see how small you could make the divider, and the capacitance of the pins (and add a little more for the traces), and seeing if the rc time constant is significantly less than your clock frequiency. Short of that there are tons of buffers that will do the 5->3.3v, especially if you only need to go one way.

seems like a good on to try (you can also get 16bit versions if you are running a lot of pins) Almost any chip maker makes a part that will do what you want.

3l3ctrici7y

Sun Mar 01 2009, 06:05AM

Registered Member #1806 Joined: Sun Nov 09 2008, 04:58AM
Location: USA
Posts: 136

Speed? Interesting. Are you certain about that?

Both avr-usb

and usbtiny

use zeners to cap the 5v signals coming out of the AVR to the 3.3v expected by the usb host controller on it's data lines. Those are low speed devices, so the zeners must be functioning reasonably well at 1.5 Mbps.

My understanding of the issue of the speed of a diode has to do with the reverse recovery time, where it will conduct in reverse bias for a moment before becoming mostly non-conductive after having been in forward bias. In that case, it is having charge reversal across the junction. A zener used for voltage regulation, is always in reverse bias. There is no forward current to recover from. I don't think there will be any speed issues like diodes used as rectifiers have.

This is my understanding of the situation, and I don't know of anything that conflicts with what I have said.
If someone knows for a fact that anything I have said is wrong, please do inform me such that I will be correct in the future.

Bjørn

Sun Mar 01 2009, 02:25PM

Registered Member #27 Joined: Fri Feb 03 2006, 02:20AM
Location: Hyperborea
Posts: 2058

Why does the RAM have TTL compatible input levels and CMOS compatible output levels, are you sure that the output is 5V?

In some cases you can use series resistors and rely entirely on the diodes built into the FPGA to limit the voltage. If your FPGA is really expensive you might consider doing it the proper way instead.

MRacerxdl

Sun Mar 01 2009, 05:32PM

Registered Member #989 Joined: Sat Sept 08 2007, 02:15AM
Location: SÃ£o Paulo, Brazil
Posts: 476

My board is that:

The FPGA software is running from 16Mhz but the clock is managed to reach 66.667Mhz, but I dont think I can push 66Mhz from a old DRAM from EDO PC Memory.

About the internal diodes, good thing, I havent think about see on the fpga datasheet if it have internal clamp diodes.

In this AVR Usb I see two diodes in series to drop the voltage to 3.8V, maybe if I put three 1n4148 in series with the datasignals? 3 * 0,6 - 1,8 and 5 - 1,8 = 3,2V

Bjørn

Sun Mar 01 2009, 06:52PM

Registered Member #27 Joined: Fri Feb 03 2006, 02:20AM
Location: Hyperborea
Posts: 2058

I found the answer at the Xilinx website (assuming that Spartan 3A is not very different):

Spartan-3/-3E I/O can be made 5V-tolerant by using an external series current-limiting resistor to limit the current into the upper clamp diode to 10 mA. This makes the input 5V-tolerant, but an I/O configured as an output still cannot drive 5 Volts and the resulting VOH does not meet the input specifications of the 5V device.

Steve Conner

Sun Mar 01 2009, 10:02PM

Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706

I've used the series resistor method when interfacing to XScale chips. I actually prefer a potential divider to a single resistor, as it can eliminate current in the clamp diode altogether. All CMOS chips have clamp diodes for ESD protection, there is no question whether your FPGA will have them.

Going the other way, 74HCT series logic will boost a 3.3V signal up to drive a non-TTL-compatible 5V input.

Diodes in series with data lines will not work, with CMOS logic at least. I leave it as an exercise to the student to figure out why. :P

Regardless, I'd just get 3.3V RAM chips to save hassle. Getting signal timings right on DRAMs is quite hard enough, and I expect putting resistors in series with things would screw the timing up completely. 3.3V DRAM is just as obsolete as 5V and should be available at a garbage dump near you.

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