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wind interface box: a circuit to divert excess current when a certain voltage is exceeded

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Dr. Slack

Sun Dec 14 2008, 11:47AM

Registered Member #72 Joined: Thu Feb 09 2006, 08:29AM
Location: UK St. Albans
Posts: 1659

Yes, you have just discovered the joys of linear circuits. Running the FETs in linear mode means they have gain, going up to surprisingly high frequencies. All it takes is long wires on some of the terminals to create enough coupling to make an oscillator, you don't actually have to add explicit inductors, transformers and things. All the clues were in your previous post, any time you measure what should be a DC circuit and the DMM gives nonsense results, suspect oscillation. The reason is that adding the DMM, or body capacitance to various nodes, changes the conditions, so the thing's all over the place as you probe it. This is why a scope is such a useful bit of kit, even if you never intend making an oscillator. Power supplies are very common circuits for this, anytime you have a regulator with mysteriously rubbish regulation, suspect oscillation.

The 10R resistor in series with the gate is actually a standard trick used by RF engineers to stop oscillation, it's called a "gate stopper" (or "base stopper" for bipolars), and 10R is actually a very common value. What it does is reduce the high frequency gain, so the circuit continues to work at low freuqency, but doesn't have the high frequency gain to honk through the parasitic components that are the leads and the device capacitances.

When a device has enough gain to honk like this, it can be very counter-intuitive trying to stop it. Adding capacitors to ground from hot nodes, that you think might load the signal, can atually make things worse by improving the tuned circuit Q. Adding loss, as you found out, will usually work. What made you try such a component incidentally, it's a very good solution? Although the oscillation has stopped for now, changing the lengths of leads to your windmill could revive it, as could tidying it up and putting it in a box or changing the FET current, so you probably need a more robust solution.

I'm not an RF engineer, so I won't start suggesting where to put other remedies, and certainly not blind. Perhaps you could post a diagram of your setup, including *all* decoupling caps, leads *and their lengths* *and the area they enclose*, and then some of the RF experienced guys (they know who they are) could offer some suggestions. This trick is going to be "taming" these external circuits so they look resisitve where the FET has gain, and only look like high Q reactive components at frequencies way above where the FET has run out of steam. You have the advantage that you can put resistors everywhere, without changing your 0% efficiency, a luxury that designers of other applications do not have. You are not going to be designing the external circuit as such, but methods for making sure that the FET doesn't "see" the external circuits, suitable lossy filters so that you can do pretty much what you like externally, while everything in the regulator will be tame.

BTW, if you were to build the power relaxation oscillator of a few post ago, then oscillations cannot happen in a FET that's either on or off, but that's a different solution to the problem.

IamSmooth

Mon Dec 15 2008, 02:45AM

Registered Member #190 Joined: Fri Feb 17 2006, 12:00AM
Location:
Posts: 1567

Based on your comment I googled this article:

The 10 ohm value was a guess at something to dampen oscillation without dropping too much voltage.

Dr. Dark Current

Mon Dec 15 2008, 07:31AM

Registered Member #152 Joined: Sun Feb 12 2006, 03:36PM
Location: Czech Rep.
Posts: 3384

Why not use something like 1000 ohms? The gate is capacitive so it really does not drop any voltage, it just makes charging/discharging it slower, and this way you could be sure no oscillations will happen.

Dr. Slack

Mon Dec 15 2008, 08:12AM

Registered Member #72 Joined: Thu Feb 09 2006, 08:29AM
Location: UK St. Albans
Posts: 1659

A good find! So oscillation is inherent in the paralleled FET connection, and doesn't require nasty external lead impedances at all. And of course while an on or off FET won't honk, during the transition it's in the linear region, so will.

While increasing the gate resistors will further decrease the high frequency gain (they work as an RC into the gain-enhanced Miller capacitance of the drain-gate junction), they will reduce the speed, and set up the potential for a much lower frequency oscillation (which was the first one you were concerned about) which is an interaction with other delays in the circuit such as the generator impedance and the rail capacitance. It might be a good idea to model the whole circuit to see if this effect is going to be a problem. Either use SPICE or a clone (see the wiki for simulators), or put a representative rail capacitor on and feed the rail through a few ohms to model the generator output impedance in hardware, or drive it from the generator itself (perhaps at low speed, it should be fairly linear). Increase the gate resistors and see if anything goes off at a lower frequency.

IamSmooth

Mon Dec 15 2008, 02:58PM

Registered Member #190 Joined: Fri Feb 17 2006, 12:00AM
Location:
Posts: 1567

I am adding ferrite beads as the article suggests. Right now I have one 10ohm resistor at the junction where my wire splits to the eight mosfets. Is it better to have one 10 ohm resistor right before the gate of each mosfet? I figure that if I just have one then all the mosfets see the same resistance; if I use one on each mosfet, even if they are precision resistors, the slight difference might affect the simultaneous turn-on timing among them.

Dr. Slack

Mon Dec 15 2008, 04:24PM

Registered Member #72 Joined: Thu Feb 09 2006, 08:29AM
Location: UK St. Albans
Posts: 1659

You should have a seperate resistor for each gate to isolate the gates from each other, it's the low impedance between FET gates causing the problem (according to your article). Similarly, added ferrite beads should be one per gate. This is not a switching application, so "turn-on" timing is not an issue. Any slight difference in speed between the FETs is similarly almost irrelevant in this linear use as the long term heating load is forced to share by the source resistors (you do have one source resistor per FET?). As Dr Kilovolt points out, this circuit would work almost identically with 10R or 1000R on each gate as the speed is so low, so variations around 10R due to resistor value tolerance can be ignored.

GeordieBoy

Mon Dec 15 2008, 05:40PM

Registered Member #1232 Joined: Wed Jan 16 2008, 10:53PM
Location: Doon tha Toon!
Posts: 881

Be careful when paralleling MOSFETs intended for switched-mode duty, in linear applications! The negative temperature coefficient of the gate-source threshold voltage Vgs(th) means that the hotest devices become enhanced the most if a fixed gate voltage is applied to all devices. This can cause the hottest device to carry the lion's share of the load current leading to thermal runaway. It is normal to use active current sharing schemes like the one on page 4 of this paper to force MOSFETs to share current in linear active loads:

-Richie,

Dr. Slack

Tue Dec 16 2008, 10:14AM

Registered Member #72 Joined: Thu Feb 09 2006, 08:29AM
Location: UK St. Albans
Posts: 1659

Richie wrote:

It is normal to use active current sharing schemes like the one on page 4 of this paper to force MOSFETs to share current in linear active loads:

Dr. Slack wrote:

the long term heating load is forced to share by the source resistors (you do have one source resistor per FET?).

Perhaps that should have been worded "encouraged to share". Simply using a seperate source resistor per FET and driving the gate resistor in parallel won't force the currents to share quite as well as using an op-amp + source resistor as in Richie's document. The sharing will be unequal to the extent that Vgs is unequal. Thus at very low currents, differences in Vgs could be comparable to the drop across each source resistor, and sharing could be very unequal, but at low currents and so low dissipiation, who cares? As the current gets bigger and sharing matters, the sharing ratio improves as the IR drop dwarfs differences in Vgs. The extra complication involved in using the op-amps (to power them, more things to go wrong, more complexity) is probably best avoided if possible.

Dr. Slack

Thu Dec 18 2008, 11:50AM

Registered Member #72 Joined: Thu Feb 09 2006, 08:29AM
Location: UK St. Albans
Posts: 1659

48 hours. After all I've learnt about paralleling stuff, I've put a pathetic wiki page start up. Mr Smooth, would you add the link to the parallel instability artcile you found to it please.

IamSmooth

Sun Dec 28 2008, 04:43AM

Registered Member #190 Joined: Fri Feb 17 2006, 12:00AM
Location:
Posts: 1567

I just wanted to update everyone that I added the ferrite beads and gate resistors. I used beads with suitable resistance at 40-300MHz, and I added 10 ohms 1% resistors to each gate. The shunt regulator used 8 500watt mosfets and worked perfectly. I ran my generator with a 1.75hp motor and the regulator kicked in at the set voltage of 200v. The voltage never exceeded the setting and shunted the current to my dump load. I rigged two DC fans in series and connected it across the load. They have a range of about 20v-56v, so they ramped up nicely with the increasing load to cool off the fets.

This device is a safety mechanism in case I lose the grid connection for my wind generator and the inverter load disappears. Without the load the open voltage could exceed the inverter's maximum input voltage and destroy it when the grid becomes active again.

I have one concern about the negative Vgs(th) temperator coefficient. Is it inevitable that one FET will eventually take all the current if I leave the device active for a prolonged period? Will this happen if I have fans cooling them and operate each at no more than 200W?

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