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wind interface box: a circuit to divert excess current when a certain voltage is exceeded

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IamSmooth

Sun Nov 23 2008, 01:54AM

Registered Member #190 Joined: Fri Feb 17 2006, 12:00AM
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Dr. Slack wrote ...

If you have 1watt 100v zeners, then allocating 300mW to heating at max current is very conservative. At the maximum 12v on D5, that's 3mA, so choose D5 = 3.9k.

The voltage-drop zeners D1 in series with D2 is a very low impedance, and will destroy thenselves in a moment under over-voltage conditions, so R7 is to limit the fault curent that can flow. Obviously it reduces regulation. To get 8A shunt current you need 8v change on the rail without R7. If R7 = 3.9k as well you now need 16v delta to get 8A shunt.

How do you figure there is 300mW of power going through the zener?

With 13v across D2 and 3ma through it I need a R5 of 4.3k to maintain the 13v. If I choose the same for R7 this will limit I to 3ma through D1 (my string of 5 100v/1W zeners). This is just 0.3W through each zener. Was the choice of 300mW an arbitrary value well below the maximum wattage rating?

IamSmooth

Mon Nov 24 2008, 02:10AM

Registered Member #190 Joined: Fri Feb 17 2006, 12:00AM
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I apologize for a double-post.

I just would like you to know that I'm getting the components this week. I strapped together an 8A/600v mosfet I had lying around and set the Gm to a 0.2 using 5ohm source resistor. I set the gate zener to 13v and put a 7.5v zener/4.3k resistor above it in series connected to my voltage source. I used a 100ohm/10W resistor for my load. It was wonderful to see that for every 0.1v increase on the Rsource I could see 0.2*0.1v increase in the load amperage, just as you said it would. The only thing missing was the R5 resistor which didn't seem to make a difference. I am still not sure how this helps. Is there an experiment I can run with some low voltages to see the difference it is suppose to make?

Dr. Slack

Mon Nov 24 2008, 08:07AM

Registered Member #72 Joined: Thu Feb 09 2006, 08:29AM
Location: UK St. Albans
Posts: 1659

I think my biggest error so far is in identifying R5 as nice to have. It's actually essential. When the rail voltage rises, the zeners conduct and send charge into the FET gates. When the rail voltage falls, the zeners turn off, and the gate charge just sits there, with nothing to bleed it off. If the power devices were bipolars, then their base current would pull charge off this node, but FETs will not. However, the gate capacitance is very small, so a bit of board leakage, a finger-print on the FET package, or a meter from gate to ground could make it work properly. Having a small value like several kohms will make it turn off fairly quickly, I was thinking stability and keeping the speed of the shunt up. However, having it turn off really slowly through leakage or whatever is not really a problem in your application. What could be a problem is when that leakage stops through cleaning the board, or when the leakage across the high voltage zeners or the board material they are mounted on (any hygroscopic board surface contaminant (like sweat salt from finger prints) will attract moisture and render the surface slightly conductive) overwhelms whatever discharge path you happen to have from gates to ground.

Is 300mW an arbitrary figure? Absolutely. The clue is the word "allocate" in the previous post. If you aim to run a component at well below its max, then you can quit worrying about it, even with very approximate calculations. If you are running yoour 100W resistors at 100W, then you'd better make sure that a) you have met all the cooling requirements like lead length, use of grease, heatsink/ambient temperature under all conditions and b) that your expected dissipation is really a max and not a typical. More so with your silicon.

Steve Conner

Mon Nov 24 2008, 09:56AM

Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706

I don't know if it helps, but I built this very device for the exact same purpose as part of my PhD research. The only difference is that mine was meant for a 24V bus instead of 600.

I used a bank of power MOSFETs and those big gold metal cased resistors, with the FETs controlled by a TL431 shunt regulator IC. The schematics are in some appendix of my thesis, but they're really not that different to what Dr. Slack is proposing.

Finally, bear in mind that both BJTs and MOSFETs suffer from current hogging in high-voltage, low-current linear use. This may limit the actual dissipation you can use to well below the datasheet rated dissipation, maybe an order of magnitude below. APT have application notes, and special MOSFETs designed for linear use that cost a fortune.

The resistors help, because they limit the maximum dissipation in the MOSFET bank to one-quarter of what it would be without them.

(If we size our resistors to dissipate 1kW at 500V, then the maximum dissipation in the FETs will be at half power, at which point half of the power is dissipated in the resistors, so the FETs dissipate 250W with 250V drop. At the 1kW level, the FETs dissipate practically nothing.)

Dr. Slack

Mon Nov 24 2008, 12:21PM

Registered Member #72 Joined: Thu Feb 09 2006, 08:29AM
Location: UK St. Albans
Posts: 1659

Finally, bear in mind that both BJTs and MOSFETs suffer from current hogging in high-voltage, low-current linear use.

Could you elaborate Steve? (I guess it's in the APT AP note, but without a link I'm not certain I want to go and look)

Is this when one device hogs the current of its directly parallel connected neighbours? If so, that's what the source resistors are for, to control the current in each device (give or take Vgsth). Obviously there has to be enoguh voltage across resistor to dominate the Vgsth differences. Perhaps I've guessed a little low. With the purpose of the circuit being to waste power, these can be larger than I've suggested. Although excess power due to hogging due to mismatch only gets to be a problem at high power, when the source resistor voltage drop is highest.

Or is it something intrinsic to the device itself? In this case it should be on the data sheet somewhere, but maybe hidden in an SOA graph rather than in the headline max V max I max power figures? As Steve says, the load resistors keep the devices out of the top righthand (high current high volts) corner of the graph.

Steve Conner

Mon Nov 24 2008, 01:49PM

Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706

VMOS FETs are made of thousands of tiny identical "cells" internally paralleled. International Rectifier's Hexfet technology is a famous example, using hexagonal cells like a honeycomb.

In switched-mode use, with high current and low voltage, the tempco of Rds(on) is positive, so the cells share current amongst themselves. But at low current the tempco flips sign, and in linear mode you also have the tempco of Vgs(th) to worry about.

The upshot is that with high enough applied voltage, the few cells with the lowest threshold voltage can go into thermal runaway and explode. (OK, I lied when I said they were "identical"...)

For the same reasons, VMOS FETs in parallel don't necessarily share current properly without source ballast resistors.

Check your MOSFET datasheet to see at what current the tempco changes sign. Linear use below this current is "At your own risk", so the lower the better. Unfortunately advances in MOSFET technology just seem to push it up. Older literature says that MOSFETs don't suffer second breakdown or need ballast resistors, and maybe that was actually true for the MOSFETs available at the time, but it isn't now.

For further reading:

oh and here is the APT appnote I referenced:

Dr. Slack

Mon Nov 24 2008, 03:24PM

Registered Member #72 Joined: Thu Feb 09 2006, 08:29AM
Location: UK St. Albans
Posts: 1659

The benefits of a posted debate are that other people have the chance to learn too, and that you have a measure of protection from my potential stupidity when others can read the thread and say "Whoa, that's dangerous/stupid/whatever".

Bingo. We probably wouldn't have learnt that through PMs. Thanks Steve.

Here's an SOA graph that I just happen to have lying around for the ifrps37n50a International Rectifier FET, 500v, 30odd amps, very low rDSon.

I guess the clue is the South-Westerly march of those pulse width lines. I'd not really thought about that feature too hard before. There's a slightly smaller gap between the 1/10mS lines than there is between 100uS/1mS, but not much. 10mS doesn't look to be anywhere near a limiting value, the graph doesn't even hint at where continuous operation might be. As the AP note says, switchmode with its short pulses is not a problem.

IamSmooth

Mon Nov 24 2008, 07:22PM

Registered Member #190 Joined: Fri Feb 17 2006, 12:00AM
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This has been a very educational thread for me guys. Thanks for the help. One last, and probably the easiest question...

The mosfets have a maximum voltage and current rating. The product is always less than the maximum power rating. How does one calculate the power being handled by the mosfet? If I have a rail-to-source load of 25ohms with 8amps (200v) going through it, and I have a source resistor to ground with 8volts and 8 amps, what numbers are used for the calculation. Is the wattage the 200v*8amps? Is it (200v+8v)*8amps?

Dr. Slack

Mon Nov 24 2008, 07:38PM

Registered Member #72 Joined: Thu Feb 09 2006, 08:29AM
Location: UK St. Albans
Posts: 1659

Neither. Power in a device is the product of volts across *it* and current through it.

So if there is 8v across the source/gnd resistors at 8A, then there's a total of 64w in those.

If there's 200v on the rail/(I think you meant)drain resistors at 8A, then there's 1600w in those.

Unfortunately you don't give the drain/source voltage, or the rail/ground voltage from which we could work it out. The total FET dissipation will be 8A * Vds. Which you need to make sure is less than the continuous SOA for your particular devices.

IamSmooth

Tue Nov 25 2008, 05:19AM

Registered Member #190 Joined: Fri Feb 17 2006, 12:00AM
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Posts: 1567

The mosfets and source resistors might need to have the heat dissapated by blowing air over their heat sinks. I have a 12v dc motor. Is there any way to connect this to the topology such that it runs when the shunt starts to conduct? I am thinking that I need to turn on a transistor to conduct to the fan, but I don't know where to put it such that
1. it is not burned from the high rail voltage
2. it does not interfere with the set points of the five mosfets

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