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Building H-bridge in progress - questions

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Tonic

Thu Mar 20 2008, 08:53AM

Registered Member #528 Joined: Fri Feb 16 2007, 10:32PM
Location: Warsaw, Poland
Posts: 166

Well, there's how bridge does look actually:

There are two waveforms without power on H-bridge. The top one is from gate, bottom from inverter output.

1206002163 528 FT0 Waveforms Nopower

And with power, you can see quite ringing:

1206002163 528 FT0 Waveforms Power

Magnified oscillograms:

1206002163 528 FT0 Magnified Waveforms1

Informations: one half-bridge has IRFP250's, second IRFP450's (at this moment I can't have four identical). The driver is based on NE555 oscillator, which's square wave is amplified by two complementary pairs of BD139/BD140. The frequency is 100-150kHz. Waveforms in higher frequencies are pretty same, but BD139/BD140 are strongly heating. Each transistor has two anti-parallel 15V Zeners and pairs of blocking Shottky diode and fast diode - with except on one transistors, which doesn't have Schottky diode (there, where red wire goes), because it was ripped out by accident

So it's shorted. The bridge power supply is just a rectify bridge, smoothing capacitors bank, which gives 1000uF at 400V and 5A fuse.

Now questions:

- why do I have crappy tops and bottoms of inverter output? I've put decoupling capacitors across + and - rails of each half-bridge - it helped nicely with transients voltages. What can I improve?

- why gate signal has rounded tops and bottoms?

- why, when I power up H-bridge, ringings occur?

- I've readed somewhere that driver must be firstly powered, then H-bridge? Is it true? Primarily bridge and transformer supplying driver had to be connected to mains, so they would be powered simultaneously

]h-bridge2.jpg[/file]
]h-bridge1.jpg[/file]
]waveforms_nopower.jpg[/file]
]waveforms_power.jpg[/file]
]magnified_waveforms1.jpg[/file]
]magnified_waveforms2.jpg[/file]

Steve Conner

Thu Mar 20 2008, 10:45AM

Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706

The ringing is caused by the stray inductances and capacitances, they get kicked into oscillation at every switching transient. To reduce it, you need to minimize the strays, and/or slow the gate drive down. It doesn't look too bad, though, I've seen much worse in my own circuits. It will get worse when you put a load on the inverter, though. (edit: as Richie mentioned, the right load can make it better!)

The rounded tops on the gate drive waveform are probably caused by the gate driver's DC block capacitor. You could try making this capacitor bigger if they bother you, but I don't think they have any bad effect on operation.

BTW, I suggest twisting the wires from your GDT to your MOSFETs together, to reduce stray inductance in the gate circuit. A 10 ohm series resistor on each gate wouldn't hurt either, close to the gate pins. It helps reduce the risk of RF oscillations, and doesn't really slow IRFP460s up too much.

Dr. Dark Current

Thu Mar 20 2008, 11:12AM

Registered Member #152 Joined: Sun Feb 12 2006, 03:36PM
Location: Czech Rep.
Posts: 3384

I hope your white/yellow GDT core does not come from a switching power supply choke.

GeordieBoy

Thu Mar 20 2008, 11:41AM

Registered Member #1232 Joined: Wed Jan 16 2008, 10:53PM
Location: Doon tha Toon!
Posts: 881

When a high-speed H-bridge is tested with a high supply voltage and NO LOAD it is normal to see this ringing present immediately after the switching transitions. So if your tests were done with no load I wouldn't worry about the ringing - this doesn't represent a normal operating mode for the inverter. And as Mr C said it all changes when you connect some real load anyway.

For what its worth the ringing you observe with no load is due to the current pulses required to alternately charge and discharge the MOSFET's output capacitances almost instantaneously at the switching instants. These large current spikes cause ringing in an unwanted resonant circuit formed by the MOSFET Cds and stray inductance in the supply wiring. You usually find that the level of ringing does not increase in proportion to increasing supply voltage because Cds falls with increasing Vds, so it doesn't look as bad when tested at 400V compared to 40V.

Once a light inductive load is applied this ringing goes away because the load current charges these capacitances smoothly during the deadtime.

>To reduce it, you need to minimize the strays, and/or slow the gate drive down

I'd just add that RC snubbers can also be used as a last resort to clean up waveforms, reduce EMI and increase reliability. But generally only where layout and gate drive have been optimised first.

-Richie,

Tonic

Thu Mar 20 2008, 01:21PM

Registered Member #528 Joined: Fri Feb 16 2007, 10:32PM
Location: Warsaw, Poland
Posts: 166

This core came from Ferroxcube and is made by 3C90 ferrite material.

I somehow did improve the waveforms. I didn't like rounded top/bottoms, so I tried to do something with this. Doubling DC block capacitor's capacitance, to 2uF, didn't help. But I noticed if I lower frequency to about 20-30kHz, a big step on tops shows - nearly to 0V. Further lowering frequency causes a nightmare messed waveform. Like there were many ovrlapping waveform, a lot of blurries etc. What is it?

I checked how it would work with only one complementary pair - waveform was very nice - square wave-like with little stepsm, as it should be. Next I've checked second pair and it was giving bad output, so I was twiddling with it. To be honest, I don't know what I did, but now signal from both complementary pairs is fine. But why at low frequencies it messes? Core saturation?

Anyway, I've checked bridge with 100nF capacitor load. The waveform had few big ringing sinusoidals, but I guess it's normal. One thing worries me, the whole signal was blurried, top and bottem the most. It's possible that oscilloscope probe interference it? (it's connected to this capacitor).

I will give photos as I return to hour in few hours.

And, thanks for replies!

GeordieBoy

Thu Mar 20 2008, 01:43PM

Registered Member #1232 Joined: Wed Jan 16 2008, 10:53PM
Location: Doon tha Toon!
Posts: 881

Ferrite gate-drive transformers typically only operate well over about one decade in frequency unless they are designed very carefully. Below this range you get un-acceptable droop because of excessive magnetising current, and above this range leakage inductance limits the slope of the edges.

> Anyway, I've checked bridge with 100nF capacitor load

Tonic

Fri Mar 21 2008, 09:11AM

Registered Member #528 Joined: Fri Feb 16 2007, 10:32PM
Location: Warsaw, Poland
Posts: 166

Sorry for being late, but I wasn't luck yesterday. I did blow a 5A fuse when playing with flyback and digital camera batteries have discharged :P

Anyway, there are pictures:

That's how gate signal looks now. Rise and fall times are pretty high comparing to on and off times - I set too high frequency.
1206089965 528 FT41483 Improvedgate

Guessing that Richie was worried about h-bridge being tortured by 100nF, I've decided to put 50nF. Nasty ringings, aren't they?
1206089965 528 FT41483 50nf Ringings

The bridge's output had werid small curls-likes deformations on signal slopes - see there:
Bridgeweirdoutpu

I've checked from where they comes and it turned out that one of half-bridges gives those deformations. The second half-bridge's output has clean slopes. It's hard to see on small photo, but if I had to compare, I would say that they are similiar to medusa's arms

What are they, and what can I do?

And, why the oscillograms of bridge's output are blurried? On photo you can see parts of tops, which are much more wider than rest of signal. Normally it's much wider and blurrier. Who's guilty, oscilloscope or bridge?

When you measure rise and fall time, which points do you compare? Peak to peak, or differently?

]50nf_ringings.jpg[/file]

]improvedgate.jpg[/file]

Steve Conner

Fri Mar 21 2008, 11:05AM

Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706

It doesn't matter if it's 50nF or 100nF, or what. A voltage-fed inverter like this is not designed to drive a capacitive load at all! Use a resistive load (light bulb) or an inductive load for testing instead, just anything except a capacitor

GeordieBoy

Fri Mar 21 2008, 06:03PM

Registered Member #1232 Joined: Wed Jan 16 2008, 10:53PM
Location: Doon tha Toon!
Posts: 881

A 100W filament lamp with long flying leads has just the right combination of resistance and inductance for low power testing!

...as long as you don't twist the leads together

The ripples on the rising and falling edges of the inverter output voltage can be due to many things... one of which is incomplete slew of the voltage to the opposite rail during deadtime - Visible in the last scope trace at the bottom of this page:

-Richie,

Tonic

Fri Mar 21 2008, 08:06PM

Registered Member #528 Joined: Fri Feb 16 2007, 10:32PM
Location: Warsaw, Poland
Posts: 166

With long flying leads you mean leads that are used to plug to power?

Actually I've tested with ordinary 75W light bulb, and it was a bit scary, hehe. I'm used to see bulbs plugged to 230V and emiiting a lot of light. With a low voltage, 30-50V, there was only orange heating filament. I was afraid it will blow glass, so I did put it inside jar and "sealed" and put safety goggles

I've tested to 47V, just before variac starts to hum dangerously. The bridge output didn't change at all, so I guess it's working fine so far. Next step will be another variac with 50V-350V scale. But since it's a monster (2.2kW!), I'm a bit afraid and I have question regarding it - must it be connected to ground?

1206129791 528 FT41483 Bulb Tests

Another question, when I plug osciloscope probe to gate, both oscillograms (of gate and bridge output) screws up. Is it normal?

Again another question - I've asked before, but I guess it was too trivial to answer

Between which points do I measure fall and rise times?
]bulb_tests.jpg[/file]
]variac.jpg[/file]

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