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Goldilocks Gate Drive?

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Steve Conner

Mon Jan 28 2008, 11:19AM

Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706

The topic of this thread is gate drive that's not too fast, not too slow, but just right

In the OMG Induction Heater thread

we discussed the possibility that "as fast as you can" is not always the right speed to drive MOSFETs or IGBTs. Gate drive chips have got more powerful over the years, devices have got lower gate capacitance, and hobbyists have got better at building really powerful gate drivers with low stray inductance.

So maybe they are too powerful? As far as I know, the main hazards are:

turning a device off very fast when it's conducting a high current. This results in a large L*di/dt voltage across any stray inductances in the circuit which can avalanche things, and

turning a device on very fast when its neighbour's antiparallel diode is conducting a high current. This causes a large forced recovery current spike, which has the same bad effects as shoot-through, because to all intents and purposes it is shoot-through.

Discuss...

ragnar

Mon Jan 28 2008, 12:52PM

Registered Member #63 Joined: Thu Feb 09 2006, 06:18AM
Location:
Posts: 1425

The harder you drive your gate, the better you will splatter the surrounding spectrum, including your nearby oscillator chips and op-amps. (Thank god for guard rings).

WaveRider

Mon Jan 28 2008, 03:34PM

Registered Member #29 Joined: Fri Feb 03 2006, 09:00AM
Location: Hasselt, Belgium
Posts: 500

I solve this problem with a judiciously chosen low-inductance series gate-resistor to increase rise/fall times a little but as well as damp out VHF oscillations that can occur with RF MOSFETS...

Experimentonomen

Mon Jan 28 2008, 04:06PM

Registered Member #941 Joined: Sun Aug 05 2007, 10:09AM
Location: in a swedish junk pile
Posts: 497

RC snubbers between D and S also help alittle.

Marko

Mon Jan 28 2008, 05:37PM

Registered Member #89 Joined: Thu Feb 09 2006, 02:40PM
Location: Zadar, Croatia
Posts: 3145

Well I think best formulation of the question would be ''can too fast gate drive really cause unexpected and mysterious semiconductor deaths at well below their datasheet ratings?''.

I really don't know a way, since things like recovery current, switching loss and avalanching just heat the device, and shouldn't destroy the device so easily as power is carefully turned up. Gate can eb killed by overvoltage but it is in most cases clamped quite well by diodes.

Richie said he would elaborate this, and I'd really appreciate that.

One of examples I'd want to point out, people like to build things like these:

I know inverter output cos fi is poor with output shorted (since leakage inductance is only thing limiting the current there), but according to jmartis it was still nowhere close to the rating.

Nobody was able to figure out the cause of failures, and I bet there are lots more of people with same problems.

Heating can be treacherous, but treacherous enough that device overheats (in no-pulsed power app) while it's case is still cold to touch?

I just hope to revive some interest,

Marko

Dr. Dark Current

Mon Jan 28 2008, 06:18PM

Registered Member #152 Joined: Sun Feb 12 2006, 03:36PM
Location: Czech Rep.
Posts: 3384

I just had an idea.. If the gate is discharged too fast, maybe it causes the area that conducts current in the silicon die to "shrink" quickly - that just before the device stops conducting, at this very moment the current flows in just a very little point in the die which causes local overheating (maybe similar to second breakdown in BJTs). I don't know the internal construction of these devices so maybe it's off.

Just an idea..

J.M.

Mates

Mon Jan 28 2008, 06:51PM

Registered Member #1025 Joined: Sun Sept 23 2007, 07:53PM
Location: Czech Rep.
Posts: 566

Since my silicon cemetery is quite big I'm very pleased about this discussion. My opinion is that the death of the "cold" FET is mainly due to over-voltage spikes. The argument that the gate can be directly destroyed by the driving circuit does not seem to me likely, since I've never destroyed a FET (or IGBT) just by driving it against dummy load (resistor) no matter how hard the switching was.

After I started to use TVS my transistors deaths became to be minimal and I'm using no gate resistor, always trying to keep the wave as square as possible. The important point here is that I have the experience that only by paralleling more than five (ideally 10) TVS makes the real protection job (they seems to work much faster). It also explains why the integrated avalange mode does not protect the transistor - it is simply too slow for very rapid and high spikes, mainly when the transistor gets hot by prolonged operation...

Dr. Dark Current

Mon Jan 28 2008, 07:14PM

Registered Member #152 Joined: Sun Feb 12 2006, 03:36PM
Location: Czech Rep.
Posts: 3384

Mates- I think spikes are not such big problem. I've destroyed 600V IGBTs with 320V supply voltage. I've used high quality MKP decoupling caps and ultrafast reverse diodes. The spikes could not have been higher than a few volts...

Marko

Mon Jan 28 2008, 07:24PM

Registered Member #89 Joined: Thu Feb 09 2006, 02:40PM
Location: Zadar, Croatia
Posts: 3145

Aww, what time is this ''voltage spikes'' are blamed for failures.. :) At least this is from my understanding.. Hope not to get too far away from the thread;

Mates: your flyback topologies run at constant power and high voltages with lots of energy are created at turnoff, and in cases of SSTC's only way for you to get rid of that energy is to convert it into heat. TVS just move it from the IGBT so it doesn't get destroyed.

This loss will be *the same* no matter the speed you turn the IGBT off.

It is heat that kills the IGBT's, avalanching itself just causes lots of energy to be turned into heat.

Nothing like that can happen with a bridge no matter what's the load since diodes clamp any over voltage to supply rails. Diode recovery may cause small humps to appear but they are very low energy and easily absorbed by device or a small TVS.

Miller capacitance can transfer voltage spikes to gate which are dangerous there, because gate is dielectric and very little energy is enough to blow it up; only clamping helps at that point.

Still it'd probably be better for me now to shut up and read...

Marko

uzzors2k

Mon Jan 28 2008, 08:00PM

Registered Member #95 Joined: Thu Feb 09 2006, 04:57PM
Location: Norway
Posts: 1308

You might be onto something with capacitances Marko. Usually we're hard-switching when running flybacks and non-feedback SSTCs, in which case the voltage across the devices at turn-on is maximal. With slowish gate drive the resistance of the switching device will increase slowly, whilst discharging the output capacitance equally slow at the same time, and thus keeping currents low. By the time the device is fully on the output capacitance will be almost discharged. With insane 30A gate drive on 2nF of gate capacitances the switch might turn on so fast that the output capacitance is still fully charged (nearly) by the time the switch is at minimal resistance. Say 0.2 ohms versus 320V, those are DRSSTC/ coilgun current levels! With the peak current rating of the device exceeded 100 thousand times a second eventually something will have to go.

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