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Registered Member #187
Joined: Thu Feb 16 2006, 02:54PM
Location: Central Ohio
Posts: 140
... wrote ... Really all that is necesary to make the mosfets share a load gracefully is to add a large amout of resistance in series with the drain...
Hmm... What if you are parallel-ing the mosfets because you want to reduce the resistance and get more current? Seems like this technique is counter productive.
Registered Member #56
Joined: Thu Feb 09 2006, 05:02AM
Location: Southern Califorina, USA
Posts: 2445
The technique works both when running in the linear mode (as IamSmooth is proposing) and when running in saturation (as is normally the case). When running the fets in saturation the variations in Rds are very small, usually not more than a few hundred micro ohms to a few miliohms depending on the device, so only a very small amount of series resistance is needed.
In this application the transistors are only being paralleled to allow for a large overall power dissipation, and the fets are never driven into saturation, so adding series resistance simple reduces power consumption in fets.
Registered Member #30
Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706
I still don't think adding resistance in series with the drain would work well. The drain has a very high impedance and looks like a constant current sink. If you're putting resistance somewhere, it ought to be ballast on the source, so the voltage drop across it appears in series with Vgs.
Registered Member #72
Joined: Thu Feb 09 2006, 08:29AM
Location: UK St. Albans
Posts: 1659
I am only disagreeing with Steve Conner's definition of the problem, not his solution. It's perhaps worth being picky about the difference, in case someone tries to extrapolate these suggestions to a different case.
If the goal is to make the FETs *share current* roughly equally in the linear mode, then the ballast resistors must go in the source, for exactly the same reason that ballast resistors in the BJT case go in the emitter. It provides negative feedback as its voltage drop reduces the Vbe or the Vgs.
If the problem is to avoid the greediest (lowest Vth) FET going bang because unequal current sharing in the linear mode caused it to take excess current, then drain resistors *will* acheive that, by limiting the dissipation of each FET individually. However, the amps per volt, or transconductance, of the set of FETs and resistors will be non-linear. If the current is around the middle of FSD, then some FETs may have already saturated and some will be yet to come on. These will contribute nothing to the transconductance. Thus as the Vgs rises different FETs, and different numbers of FETs, will control the transconductance. This is not necessarily a problem in a simple voltage clamp, but if you want programmable current drawn, or you want stability with it in a loop, then you may have problems.
Source resistors, as they also provide negative feedback, will stabilise the transconductance.
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mosfets vs power transistors
