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Question on Steve W's DRSSTC Controller

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Josh Johnson

Tue Jan 08 2008, 10:21PM

Registered Member #793 Joined: Sun May 20 2007, 06:50PM
Location: Minneapolis, MN
Posts: 35

I was hoping some of you could help me with a question on Steve Wards DRSSTC Controller.
http://www.stevehv.4hv.org/DRSSTC3/DRSSTC-OCDsch.JPG
The J/K Flip Flop can only disable the gate drivers on a rising edge of the CLK so only half of the zero crossings are used to safely shutdown from an event (interrupter pulse ending, OCD trigger, etc.). I think allowing the triggering on either a rising or falling edge would be a better way to go because you can end oscillations as soon as possible saving the IGBTs just one more half-cycle with bad things going on such as over current.
Or is one more half-cycle no big deal?
Or am I missing something here?

Steve Ward

Tue Jan 08 2008, 10:36PM

Registered Member #146 Joined: Sun Feb 12 2006, 04:21AM
Location: Austin Tx
Posts: 1055

Yep, you are right, it has to wait in that event. At the time i figured it wasnt too critical since the current cant rise *that* quickly and the OCD is meant to detect excessive currents in normal operating conditions (not fault conditions) where the current rise is rather slow. You can use both flip-flops and set one to trigger on the other edge, but then you would have to AND the outputs together or something, which seemed like too much bother to me at the time.

Josh Johnson

Tue Jan 08 2008, 11:59PM

Registered Member #793 Joined: Sun May 20 2007, 06:50PM
Location: Minneapolis, MN
Posts: 35

Thanks for the fast response Steve. Maybe I'll incorporate the extra FF in my design.

Boomerang

Wed Jan 09 2008, 10:59AM

Registered Member #80 Joined: Thu Feb 09 2006, 11:36AM
Location: Melbourne, Australia
Posts: 4

Another thought in relation to the benefit of having synchronous turn-off for both rising or falling clock edges is that apart from marginally better performing OCD operation, there is also a minor benefit at ringdown at the end of the usual interrupter pulses.

At this point, energy is pumped back from the resonators into the bridge DC supply by rectification action of the reverse diodes in the IGBTs. If the synchronous turn off is done on only one clock edge, the same two IGBTs (in a full bridge) rectify the first (higher current) ringdown pulses every time. With a dual edge synchronous turn off system, there is a 50-50 chance as to which pair of IGBTs take the first reverse ringdown rectification cycle, thus sharing the electrical stress (so to speak). Usually this would not be worth the extra flip-flop complexity, but because most solid state coilers run IGBTs under "all they can give us" conditions, dual edge synchronous turn-off is, at least conceptually, some extra assistance to those relatively expensive lumps of silicon. Note: I don't use Steve's Controller design, but have successfully used dual edge turn-off in my own systems.

Josh Johnson

Thu Jan 10 2008, 03:39AM

Registered Member #793 Joined: Sun May 20 2007, 06:50PM
Location: Minneapolis, MN
Posts: 35

Boomerang, what technique to you use in you own design for dual edge turn off?

Boomerang

Sat Jan 12 2008, 03:28AM

Registered Member #80 Joined: Thu Feb 09 2006, 11:36AM
Location: Melbourne, Australia
Posts: 4

One implementation is shown in the schematic below (Multisim Simulation). This circuit uses an EXOR gate driven from the Main Clock to create narrow trigger pulses on both rising and falling edges (width determined by R3 & C2). Main Clock is the top trace in Sim waveforms and the dual edge trigger pulses the 2nd trace.

The Interrupter Pulse Extender circuit provides an output that has a small delay relative to the rising edge of the Interrupter input (delay determined by R2 & C1) and extends the Interrupter period at its falling edge by an amount determined by R1 & C1 (eg 2 to 3 Main Clock periods duration)

The circuit uses two D Flip Flops (74HC74). These have rising edge CLK clock inputs and active Low PRESET and CLEAR inputs.

The Interrupt input (3rd Sim trace) releases the CLR of the first FF and sets it D input Hi. The slightly delayed output of the Pulse Extender then CLKs the first FF output Hi. Its Q1bar output PRESETS the 2nd FF, setting the Clock Gating Pulse signal (Q2) Hi. When the Interrupt input goes Low, FF1 is CLEARED which in turn releases the PRESET on the 2nd FF. The 2nd FF output will then be CLKed Low (its D input is Low) synchronous with the next dual edge trigger pulse (which may be Main Clock rising or falling) as required. A short while later the Interrupt Pulse Extender output goes Low, and CLEARS both Flip Flops until the next Interrupter cycle.

Note: The Main Clock is shown running all the time in the Sim. In actual operation it is only running while the Synchronous Gating Output is Hi, of course.

1200108511 80 FT37136 Dual Edge Synchronous Gating

1200108511 80 FT37136 Sim Waveforms Falling Edge

Steve Conner

Sat Jan 12 2008, 02:37PM

Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706

My controllers also only switch full cycles of gate drive. I did this on purpose, because I was worried that they might try to generate a net DC output if they were allowed to switch half-cycles. This would saturate the GDTs and generally cause a bad day.

If the controller can only switch full cycles, then it's forced to output the same number of negative half-cycles as positive ones, so there can never be any DC.

DC might not be a problem in a DRSSTC, but I planned to use the Mk2 controller for CW SSTCs and induction heaters too.

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