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CM600 as SISG; Is it bad to leave the auxiliary emitter terminal open?

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J. Aaron Holmes

Mon Dec 31 2007, 07:59AM

Registered Member #477 Joined: Tue Jun 20 2006, 11:51PM
Location: Seattle, WA
Posts: 546

I'm desinging an SISG board for a CM600 IGBT brick. Actually, 30 of them

I picked up just short of three dozen CM600's for $5/each. So a big SISG was the obvious thing to do with them. Unfortunately, I'm a total IGBT brick newb, and also an ExpressPCB newb. Doh!

So on to the question: It seemed like the proper thing to do in this case was to simply make a board that fit directly across the main Collector/Emitter terminals and then had a place to solder on a Gate connection. The brick has an auxiliary Emitter terminal, however. Do I need to do anything with it? My intuition can't come up with any reason why I should not just leave it open, but my intuition is pretty feeble in this particular area...

Here's a quick mock-up of what the PCB layout might look like (this is for TWO boards; I'd be cutting it in half--and again, realize that this is my first time using ExpressPCB, so be nice

Cheers,
Aaron, N7OE

Finn Hammer

Mon Dec 31 2007, 09:12AM

Registered Member #205 Joined: Sat Feb 18 2006, 11:59AM
Location: SkÃ¸rping, Denmark
Posts: 741

Aron,

With up to 4500A passing trough the IGBT, one might think that *some* voltage voltage could get induced along the internal current path from external emitter pad to the die. This would tend to increase the gate voltage to a dangerous level that cannot be controlled externally.
This should OTOH not happen on the auxiliary Emitter terminal, since it only carries about 10-20A of gate turn on current.
Break a dead brick open, and you will see, that the auxiliary connection has a very long electrical path inside the brick, with associated high inductance.

I`ve tried long to figure out what this means to blown gates, but.....

FWIW, my BRISG started to function (stopped failing with blown gates), when I moved the Gate protection TVZ from auxiliary emitter pad to the power emitter pad.
Go figure.

So your layout looks good to me. It`s almost a carbon copy.

Cheers, Finn Hammer

J. Aaron Holmes

Mon Dec 31 2007, 05:17PM

Registered Member #477 Joined: Tue Jun 20 2006, 11:51PM
Location: Seattle, WA
Posts: 546

Thanks, Finn! It was your whole "BRISG" thing that got me wondering about using these in the first place.

Finn Hammer wrote ...

FWIW, my BRISG started to function (stopped failing with blown gates), when I moved the Gate protection TVZ from auxiliary emitter pad to the power emitter pad.
Go figure.

Oh good. That makes me feel a lot better! Your explanation of the emitter lead wiring is sort of what I'd expect from a look at the outside of the package. I haven't played with these enough to destroy one yet, so no excuse to break one open. As soon as the "big amps" come, though...

Thanks!
Aaron, N7OE

HV Enthusiast

Mon Dec 31 2007, 06:48PM

Registered Member #15 Joined: Thu Feb 02 2006, 01:11PM
Location:
Posts: 3068

For the reasons Finn specified.
Your gate drive should connect to the terminals as specified.

Yes, they *are* there for a reason! :)

J. Aaron Holmes

Mon Dec 31 2007, 06:54PM

Registered Member #477 Joined: Tue Jun 20 2006, 11:51PM
Location: Seattle, WA
Posts: 546

EastVoltResearch wrote ...

For the reasons Finn specified.
Your gate drive should connect to the terminals as specified.

Yes, they *are* there for a reason! :)

...

Wait... I thought Finn was advocating use of the power Emitter connection instead of the auxiliary, which is what I'd hoped. Did I misunderstand? Really, the essence of my question is: Why should I bother running a wire all the way over to the auxiliary Emitter connection when my gate drive circuitry is already attached to the power Emitter, which is closer to the Gate, too. I'm mystified. In slower, lower-current applications, perhaps the added inductance of the auxiliary Emitter just doesn't matter, but otherwise it definitely seems bad.

Cheers,
Aaron, N7OE

Steve Ward

Mon Dec 31 2007, 09:05PM

Registered Member #146 Joined: Sun Feb 12 2006, 04:21AM
Location: Austin Tx
Posts: 1055

Whats bad is that when you run many thousands of amps through the power emitters inductance you get a large voltage across it. If you use that same inductance as a path for your gate drive, that large voltage shows up in series with your gate driver.

Im gonna agree with Dan and say use the Kelvin (auxiliary) emitter terminal for your gate drive. Yes the extra emitter connection has more inductance, but its only a few inches (so 10s of nH), and from what i can see, the SISG doesnt look like its too critical for gate drive stuff anyway.

From what i understand of Finn's post, he is saying he connected a TVS from the gate to the power emitter terminal, and this reduced his gate failures, but he doesnt make sound like he was using the power emitter terminal to drive the gates.

Also, be sure your copper buss work is directly in contact with the metal tabs on the CM600 brick. Dont put a stupid PCB between the IGBT terminals and the main high current connections. That is to say, mount the PCB on TOP of your buss bars. Dont count on the bolt to be a main conductor of current.

J. Aaron Holmes

Mon Dec 31 2007, 09:44PM

Registered Member #477 Joined: Tue Jun 20 2006, 11:51PM
Location: Seattle, WA
Posts: 546

Ah, ok. Thanks Steve, Dan. I think I may be finally starting to get this

Let me test myself:

So, since we're talking about the emitter, then the inductance of the power emitter terminal lead is going to tend to raise the voltage of the emitter *at the silicon* above that of the terminal at peak current. That means the voltage of the gate terminal relative to the power emitter terminal will be larger at these times than between gate an Kelvin. Is it reasonable, then, to say that putting the TVS between gate and power emitter just means it will fire more often in this case? And, if so, would it not also suffice to use a lower-voltage TVS between gate and Kelvin instead? Would that have been an alternate solution to Finn's blown-gate issue?

I'm trying to distill the common thread to these replies. Thanks for bearing with me!

Cheers,
Aaron, N7OE

Finn Hammer

Tue Jan 01 2008, 04:37PM

Registered Member #205 Joined: Sat Feb 18 2006, 11:59AM
Location: SkÃ¸rping, Denmark
Posts: 741

All,

After pondering a little over a sketch on the back of a napkin, I think our analysis of the problem is wrong.
Let`s say that the current trough the IGBT induces 10V across the internal connection from Emitter power pad and the die.
This should bring the kelvin terminal (being unburdened by current, and connected to the emitter at the die) up to +10V relative to external Emitter power pad.

Therefore, the gate voltage really should _decrease_ under the circumstances described.

Driving the gates with the emitter power pad as the reference, will tend to shut the IGBT _off_ instead of blowing the gate.

So the reason for the blown gates is another one.

Passing the high current trough the IGBT will increase the gate voltage through the (miller) kollector-gate capacitance, with an effect that overrides the emitter pad/die voltage.

However, it does make sence that the circuit started to function when I moved the TVZ from kelvin to power pad.
By doing that I saved the gate from 10V extra voltage.

It should be noted that the gate voltage is generated across the TVZ (Z4 in your board), under the influence of up to 120A during the first couple of hundreds of nS`s (depending on Fres.)
If you reference the bottom of the TVZ to the kelvin terminal rather than the emitter power pad, it is up to experiment which voltage will be generated from terminal to die.
This will appear along the longest internal connection of the brick, and one that is not designed for that kind of current. You may loose the crowbar action of the SIDAC`s.

So, Aron, do you feel lucky? ;-]

Cheers, Finn Hammer

J. Aaron Holmes

Tue Jan 01 2008, 06:06PM

Registered Member #477 Joined: Tue Jun 20 2006, 11:51PM
Location: Seattle, WA
Posts: 546

Thanks, Finn. I'm cogitating about this now... I think I finally appreciate the non-obviousness of the problem. Let me make some napkin drawings of my own and see if I can reason my way out of this corner in a subsequent post.

Finn Hammer wrote ...

So, Aron, do you feel lucky? ;-]

No.

That is, I certainly think it will be worth trying things out on a smaller scale before I hook up two dozen of these in series and bet the house!

EDIT: Maybe all this means is that only the negative end of Z4 should be connected to the power emitter and everything else should be connected to Kelvin. Still sketching guesstimated waveforms, though...

Cheers,
Aaron, N7OE

Mods, please excuse the double-post!

J. Aaron Holmes wrote ...

EDIT: Maybe all this means is that only the negative end of Z4 should be connected to the power emitter and everything else should be connected to Kelvin. Still sketching guesstimated waveforms, though...

Yes, the more I think about this, the better I like it. Please see the following blurry hand-drawn SISG schematic with my suggested alteration (sorry it's so ugly!):

K = Kelvin in the schematic, in case you wondered.

So, the idea here is that the influence of the inductance of the E and K connections internal to the brick is eliminated as much as possible. The inductance of E comes into play only during the charging of the capacitor, which is done via the path between K and E internal to the brick. At this point, the voltage of E relative to the actual E on the silicon is irrelevant, since the IGBT has not been "turned on" yet. Peak current on the E and K leads prior to IGBT turn-on is thus the peak current required to charge the capacitor. Once the IGBT is turned on, a few kA travelling C-E will pull the voltage at the E terminal down below the K terminal, however thanks to the TVS and diode, the capacitor shouldn't drain backwards or anything strange like that (as far as I can tell). Placing the gate protection TVS across G-K provides maximum immunity from inductance of the leads internal to the brick, according to prior discussion above.

Does this seem better? Guess we'll see!

Cheers,
Aaron, N7OE

Finn Hammer wrote ...

It should be noted that the gate voltage is generated across the TVZ (Z4 in your board), under the influence of up to 120A during the first couple of hundreds of nS`s (depending on Fres.)
If you reference the bottom of the TVZ to the kelvin terminal rather than the emitter power pad, it is up to experiment which voltage will be generated from terminal to die.
This will appear along the longest internal connection of the brick, and one that is not designed for that kind of current. You may loose the crowbar action of the SIDAC`s.

I think I'd failed to address this particular concern. Hmmm... It seems to me that the "crowbar effect" will simply be a bit over-eager with the SIDACs/TVSs across C-E than C-K. I mean, the SIDACs/TVSs should never register a *lower* voltage across them than what is actually at the IGBT silicon. It should always be higher, yes? Maybe I'm misunderstanding your concern.

Cheers,
Aaron, N7OE

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