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Very fast bidirectional FPGA to microcontroller interface

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Bjørn

Thu Nov 22 2007, 07:16PM

Registered Member #27 Joined: Fri Feb 03 2006, 02:20AM
Location: Hyperborea
Posts: 2058

The interface is 11 wires, two control lines, one DDR clock and 8 data bits. The maximum transfer rate from a 60 MHz LPC2119 ARM chip to a Spartan 2E FPGA is 7 MB/s, that is identical to the maximum theoretical transfer rate at 8 bit. Chips with the fast I/O feature should be able to do up to 30 MB/s.

First the address and increment is loaded, after that a transfer can be done at every clock edge. Since the data is transferred at the same time as the clock there is a shift register in the FPGA that generates a delay so the data is not captured until the data is stable. This means that the FPGA must be clocked significantly faster than the bus clock.

Video in WMV format of the FPGA acting as a video generator displaying data from the ARM:

Since the increment can be any value it is very usable for graphics and just a small change is needed to make it draw textured lines.

If anyone can improve on this Verilog code I would be very interested:
// ************************************
// CPU <--> FPGA interface (11 lines)
// d0-d7 armDataBus
// m0-m1 armMode
// clk armClock
//
// mm
// 00 write data, increment
// 01 read data, increment
// 10 load address
// 11 load increment
// ************************************

inout [7:0] armDataBus;
input armClock;
input [1:0] armMode;

reg armPrevClock;
reg [5:0] armDelay;
reg [31:0] armAddress, armIncrement;
reg [31:0] read_a;

always @(posedge clk) begin
if (armPrevClock != armClock)
begin
armDelay <=6'b001000;
armPrevClock <= armClock;
end
else
armDelay <= armDelay >> 1;

if (armDelay[0])
begin
case (armMode)
2'b00 :
begin
ram[armAddress] <= armDataBus;
armAddress <= armAddress + armIncrement;
end
2'b01 : armAddress <= armAddress + armIncrement;
2'b10 : armAddress <= {armAddress[23:0], armDataBus};
2'b11 : armIncrement <= {armIncrement[23:0], armDataBus};
endcase
end
read_a <= armAddress;
end
assign armDataBus = (armMode == 2'b01) ? ram[read_a] : 8'hzz;

Carbon_Rod

Fri Nov 23 2007, 06:21PM

Registered Member #65 Joined: Thu Feb 09 2006, 06:43AM
Location:
Posts: 1155

FPGAs are cheap now, but the Altium designer is still way over priced.

Is it a PCI express card design?

Interesting, you could use a few of these too

Bjørn

Fri Nov 23 2007, 06:39PM

Registered Member #27 Joined: Fri Feb 03 2006, 02:20AM
Location: Hyperborea
Posts: 2058

I am using a card from here:

and Xilinx webpack software, it is free but a 3GB download and I used 30 seconds to crash it.

It is part of a series of experiments in an attempt to develop a powerful and useful computer that costs $50 or less. Useful means it would be able to run a webbrowser/MP3 player and at the same time sample/generate signals at 100MHz or more.

Tom540

Fri Nov 23 2007, 08:52PM

Banned on 3/17/2009.
Registered Member #487 Joined: Sun Jul 09 2006, 01:22AM
Location:
Posts: 617

Whoa that sounds pretty tough. Use a Basic Stamp 2. lol I use the webpack a little too but I only fiddle with the schematic based designs for now. I'm pretty much a noob.

Carbon_Rod

Sat Nov 24 2007, 02:36AM

Registered Member #65 Joined: Thu Feb 09 2006, 06:43AM
Location:
Posts: 1155

BjÃ¸rn,
Have you reviewed the 64bit RISC core f-CPU project files yet?

IIRC the group also released a GCC tool chain.

Steve Conner

Sat Nov 24 2007, 12:20PM

Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706

That looks pretty cool, Bjoern, as does your $50 computer project! I'd love to make some sort of intelligent comment, but I know next to nothing about FPGAs and HDLs.

Did you ever check out the XScale processors? I started using the PXA270 at work, and I've been amazed by how much they will do. They are basically ARMs with loads of nice on-chip peripherals, including a LCD controller that can drive a SVGA monitor, and a clock speed variable between 100 and 500MHz.

Bjørn

Sat Nov 24 2007, 02:58PM

Registered Member #27 Joined: Fri Feb 03 2006, 02:20AM
Location: Hyperborea
Posts: 2058

Have you reviewed the 64bit RISC core f-CPU project files yet?

I have hade quick look at it now but it did not appear to have the clean and simple properties I am looking for.

Did you ever check out the XScale processors? I started using the PXA270 at work, and I've been amazed by how much they will do.

I have and one of those can easily run a desktop computer. The main problem is that modern chips of that type tend to be mainly BGA.

Dr. Slack

Sat Nov 24 2007, 06:30PM

Registered Member #72 Joined: Thu Feb 09 2006, 08:29AM
Location: UK St. Albans
Posts: 1659

We've just started a project at work which needs a bit of fast DSP tightly coupled to a modest control processor. We've bought a Xilinx Spartan 3 1600E software dev board for IIRC $299, which comes with a 32 bit soft processor core IP and the license to sell stuff built with it, C compiler, IDE if you like that sort of thing, etc etc. The Spartan is their cheap range, we're talking a $10 chip with a 200MHz clock, with a fair bit of logic (15% going on the processor core), multipliers and dual port RAMs. Most of the big pinout packages are BGA, but they do a 100 pin thin quad flat pack. The CPU can be parameterised, choose to implement an IEEE FPU or not, loosely (general purpose 32 bit port) or tightly (FIFOs coupled into the data address generators) couple your own custom IP into the processor. The standard board clocks the CPU at 50MHz, but it should build quicker than that (but not the full 200MHz of the DSP).

If you want a processor and FPGA, then you could do a lot worse than put them in the same cheap chip. I think Altera do something similar.

They also do a "Pico" core, which fits in a 1k memory, and is perhaps more use for implementing a PIC assembly like task.

Bjørn

Sat Nov 24 2007, 11:21PM

Registered Member #27 Joined: Fri Feb 03 2006, 02:20AM
Location: Hyperborea
Posts: 2058

I have considered keeping everything in the FPGA. Performance is a slight problem, but the main problem is that complex FPGA projects soon stops being fun. The Xilinx software is rather like working blindfolded.

The reason for the fun requirement is that when it stops being fun such projects soon gets abandoned.

Steve Conner

Sun Nov 25 2007, 12:25AM

Registered Member #30 Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706

Yes, good point about the BGA, the latest invention to discourage home building :( We're currently buying our PXA270s already soldered to a small board that fits in a SODIMM socket. The board also has 64MB of SRAM, 32MB flash (both in BGAs too!) and a tiny DC-DC converter.

At my last workplace, we had no way to handle BGAs and didn't want to buy ready-made daughterboards, so I ended up using fairly low-end chips...

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