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Registered Member #512
Joined: Sat Feb 10 2007, 05:42PM
Location: Chico, CA
Posts: 25
Hello. My name is Rick. I'm a brand new member, and a beginner solid state coiler. I'm trying to reproduce Steve Ward's DRSSTC 2. Before I start building, I wanted to understand/simulate his interrupt and driver circuitry. I am using workbench multisim 9.0 to simulate his basic interrupter found on his design guide. I'm inputting a 42 kHz sine wave to simulate the feedback from the coil, and observing the output of the JK flip flop with the multisim O-scope.
The problem is that the output ~Q goes high for a few periods, and then stays low (much like a 1-shot). Initially I believed the problem maybe the astable 555 (the one with 2 POTS) since it wasn't changing states, I replaced with a different configurations, but then ~Q stays on the high state.
From my understanding Steve's design is supposed to clip the feedback sine wave, add some hysteresis, and pass it through the JKFF, which is configured to be a T FF since both the inputs are tied high. With the input at the clk, wouldn't this just cut the feedback frequency in half? The astable 555 sets the duty cycle while the comparator and 1-shot make sure it is in sync with the feedback. Feel free to correct my understanding.
I've attached the multisim circuit as well as a JPEG screen shot. Here are links just in case
Registered Member #146
Joined: Sun Feb 12 2006, 04:21AM
Location: Austin Tx
Posts: 1055
Its not a T FF, its acting as a SET. When the 555 astable is high, the ~Q output is forced high by the /clear input. When the 555 astable falls low, this then allows the FF to act as a FF, with J and K tied high (Note that K input is INVERTED!) the next clock input should force ~Q low. The only function of this flip flop is to stop gate drive at a current zero crossing (synchronizing, if you will). Your simulation has K tied low (meaning it will be a toggle FF, you DONT want this).
There are of course other ways of wiring the FF to do the same thing.
You may want to have your simulation toggle the SET once at the start of your simulation, i know this is required in pspice before you try doing anything with the flip flops (supposing you want them to work properly).
Let me know if the purpose of the flip flop is still unclear to you. Also note that the clock signal (derived from the feedback) is also fed into the gate drivers. The FF only controls the ENABLE of the drivers. The result should be a train of clock pulses that is then shut down at a rising clock edge after the 555 timer falls low.
Registered Member #512
Joined: Sat Feb 10 2007, 05:42PM
Location: Chico, CA
Posts: 25
thanks steve. I'll change the pins on the JKFF.
There are 3 pots on the circuit . Around what values did you set those to?
Also I wanted to use just your basic interrupter found in your design guide with the bigger EUPEC IGBTs. In other words, I don't plan on using the boost converter found under the DRRSTC2 section. The mosfet drivers will be connected to the 1:2:2 GDT and then to the half bridge. Do you think this will work okay?
Registered Member #146
Joined: Sun Feb 12 2006, 04:21AM
Location: Austin Tx
Posts: 1055
Your setup sounds OK. Really, though, its hard to drive big IGBTs with a GDT. You will probably want to parallel more gate drivers on the output.
As to the pot settings, they are supposed to work at very wide ranges. The only one that should be "set" is the pot that sets the Vref on the LM311 comparator (this sets the current limit level). If you know the ratio of your CT, the burden resistance, and the current you want to limit too, you can figure out roughly where this pot should be set. Say you have 1000A primary current max, and a 1000:1 CT ratio, that means 1A at the CT output. Say its got 10 ohms loading it, that gives 10V across the resistor. Thus, you would want to set Vref to 10V. This doesnt account for the diode drop of the full wave rectifier on the CT, so you would end up limiting too high. Its best to use trial and error.
Registered Member #512
Joined: Sat Feb 10 2007, 05:42PM
Location: Chico, CA
Posts: 25
Steve When you say place the drivers in parallel, you mean place two GDTs in parallel to drive one IGBT, and not two ti ucc37322/1 mosfet drivers in parallel to drive one GDT correct? So I would end up having to use two 37322s, each with their own GDTs, and then those GDT would be in parallel? Same for the 37321s?
What do you think is more likely to destroy the IGBTs, over current from a badly built OCD circuit, or having too high of a duty cycle from the 555? the 4hv wiki mentions that igbt failure usually occurs instantaneously, so I want to do much as possible to avoid it.
Registered Member #146
Joined: Sun Feb 12 2006, 04:21AM
Location: Austin Tx
Posts: 1055
When you say place the drivers in parallel, you mean place two GDTs in parallel to drive one IGBT, and not two ti ucc37322/1 mosfet drivers in parallel to drive one GDT correct?
No, the exact opposite. You only need 1 GDT winding per IGBT gate, but you will want higher current drive on the primary of the GDT. Paralleling windings doesnt help unless your primary has a lower impedance source. But in general, R(gdt) << R(driver) so you dont need to parallel windings or anything but you do want to parallel the gate driver chips for lower resistance on their output.
Registered Member #146
Joined: Sun Feb 12 2006, 04:21AM
Location: Austin Tx
Posts: 1055
When you say place the drivers in parallel, you mean place two GDTs in parallel to drive one IGBT, and not two ti ucc37322/1 mosfet drivers in parallel to drive one GDT correct?
No, the exact opposite. You only need 1 GDT winding per IGBT gate, but you will want higher current drive on the primary of the GDT. Paralleling windings doesnt help unless your primary has a lower impedance source. But in general, R(gdt) << R(driver) so you dont need to parallel windings or anything but you do want to parallel the gate driver chips for lower resistance on their output.
What do you think is more likely to destroy the IGBTs, over current from a badly built OCD circuit, or having too high of a duty cycle from the 555? the 4hv wiki mentions that igbt failure usually occurs instantaneously, so I want to do much as possible to avoid it.
Well... both aspects are highly controllable. You are more likely to lose an IGBT from poor bridge design, which can promote voltage spikes across the IGBTs. And of course the failure is instantaneous, its either working fine or its blown, so im not sure what the HV wiki meant by that.
In this case, you are using primary feedback (?). is it okay to use such a small gauge of wire to wrap that 1 turn considering that 2 of these transformer will go in series with the primary LC? Does this not raise the impedance?
Registered Member #154
Joined: Sun Feb 12 2006, 04:28PM
Location: Westmidlands, UK
Posts: 260
Hi Gentoo,
I beleive that picture of Steves is when he used secondary feedback, so that picture is of his secondary cable going through the ferrite core. hence the lower gauge of wire.
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DRSSTC 2 SIMULATION PROBLEMS
And don't believe anything you see in a simulation 
