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Need some help making a PCB for a full bridge

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LAN_403

dexter

Mon Jan 08 2018, 10:58AM

Registered Member #42796 Joined: Mon Jan 13 2014, 06:34PM
Location:
Posts: 195

you really need to increase the spacing between traces, especially on the HV side

|)4+80!|-|\\/

Thu Jan 11 2018, 07:17AM

Registered Member #61803 Joined: Thu Sept 21 2017, 09:18AM
Location: Bhopal,India
Posts: 34

OH,thanks all!
Is there ANYTHING else I can do to optimize this PCB??

|)4+80!|-|\\/

Sat Jan 13 2018, 02:42PM

Registered Member #61803 Joined: Thu Sept 21 2017, 09:18AM
Location: Bhopal,India
Posts: 34

|)4+80!|-|\\/

Sat Jan 13 2018, 02:51PM

Registered Member #61803 Joined: Thu Sept 21 2017, 09:18AM
Location: Bhopal,India
Posts: 34

Replying to this thread feels like poking a dead horse
Anyways,
I've made my PCB SMALLER!!!
yay!!!

1515855102 61803 FT181126 Fool Boad Bottom

|)4+80!|-|\\/

Sat Jan 13 2018, 02:51PM

Registered Member #61803 Joined: Thu Sept 21 2017, 09:18AM
Location: Bhopal,India
Posts: 34

Replying to this thread feels like poking a dead horse
Anyways,
I've made my PCB SMALLER!!!
yay!!!

1515855113 61803 FT181126 Fool Boad Bottom

Weston

Sat Jan 13 2018, 05:40PM

Registered Member #1316 Joined: Thu Feb 14 2008, 03:35AM
Location: Cambridge, MA
Posts: 365

Your clearance between traces and ground/power pours is still too small. It even seems to be touching in some places?This should be an easy setting to change in whatever CAD program you are using.

It seems your capacitor GND to MOSFET source path length increased? It seems something is weird with that part of the board. The diode appears to be on both the top and bottom layers?

Also, there is no need for the large copper pour on the output node of each halfbridge. It does not reduce leakage inductance or anything. Draw the current paths out. Most of that copper pour will have little current flowing in it.

|)4+80!|-|\\/

Sun Jan 14 2018, 01:20PM

Registered Member #61803 Joined: Thu Sept 21 2017, 09:18AM
Location: Bhopal,India
Posts: 34

I'm not sure I understand by what you mean when you say "Draw the traces out"
Also, the increased loop path was a problem found and corrected soon after the posting of the reply

Blackcurrant

Sun Jan 14 2018, 02:03PM

Registered Member #2989 Joined: Sun Jul 11 2010, 12:01AM
Location: UK
Posts: 94

Try about 2.5mm for your clearance

What's holding your mains connector and heat sinks on?
Is the blue image the top layer?
It's not clear what side components are on.
Will the PCB copper get too hot?

profdc9

Sun Jan 14 2018, 04:43PM

Registered Member #58522 Joined: Tue Mar 15 2016, 08:33PM
Location:
Posts: 50

I was wondering about this. I have not built a DRSSTC but the examples I've seen use thick copper bars (1/8 inch or greater in thickness) to conduct the current. The current is often 1000 A or more, and so you really need a stout bus for this. Even the TO-247 package IGBTs can have many hundreds of amperes of peak current. I would not have guessed that one could use thin copper to conduct this. I would think that the solder around the source and drain of the IGBTs could melt with the kind of heat that is generated from that.

For example, using Seeedstudio to make your board, they offer copper thickness up to 3 mils or 76.2 microns. Now the resistivity of copper is 1.68E-8 Ohm-m, so the sheet resistance of the copper layer is Rs=2.2E-4 ohms. Optimistically assuming your trace is 10 mm wide, the resistance is 0.022 ohms/m of trace length. That means the power dissipation, say, for an average of 20 A of current would be 8.8 W/m. This current, however, will be pushed towards the edges of the strip due to the skin effect, so that depending on the frequency, less of the cross-sectional area of the copper trace is used, so in practice the resistance of the trace could be a lot more than this, and therefore the power dissipation. For example, at 200 kHz, an average DRSSTC frequency, the skin depth of copper is 1.5 mm. Therefore probably only like 3 mm of the cross-sectional area of the strip is actually used to conduct the current, and so the actual resistance is 0.073 W/m or about 30 W/m power dissipation. This power has to be dissipated by the circuit board which is FR4 epoxy, not a good thermal conductor, and by air convection. Of course, making the area of the copper wider might help this, because of the wider area of thermal radiation and conduction.

I am really not sure of the number of W/K that can be dissipated by a copper strip by convection in air, but this seems like a lot of power to deliver to a very small volume of copper, albeit with a relatively large surface-area to volume ratio.

Like I said, I've never built a DRSSTC, but I would think that for conducting hundreds or thousands of peak amperes, one would need to use stout bus bars.

Dan

Weston

Sun Jan 14 2018, 11:14PM

Registered Member #1316 Joined: Thu Feb 14 2008, 03:35AM
Location: Cambridge, MA
Posts: 365

The current will take the shortest path and the area enclosed by this path determines the inductance, which for switching applications you want to minimize.

I drew out the path that the current will take in blue on your top/bottom layers for the last version of the PCB you posted.

As you can see, on the left, the path between the source and capacitor is lengthened by the gate trace. Also, you can see how the shortest path for the current involves little of the copper pour for the bridge outputs, so you could reduce that and have no effect on performance.

profdc9:

Actually, its worse than that. Skin depth at 200KHz is ~0.15mm (~150um). However, skin effect is generally modeled as being from the outer surface in, not from the largest dimension in, so you actually get ~ full utilization of the rectangular cross section and resistance will scale with 1/width. I think you do get some crowding on the edges of the conductor and other magnetic fields can impact the current distribution for a conductor, but surface in on every dimension is a pretty good first order approximation.

For very high current applications you will see thicker copper, solder reinforced traces, or even small bus bars soldered to the PCB. This app note

approximates the thermal resistance of a PCB trace to air as 1000C/W per cm^2 without any forced air cooling, so a hypothetical 1m x 1cm trace would have a thermal resistance of 10C/W. Capable of dissipating 8W. 20W might be pushing it though.

DRSSTCs also generally operate at a low duty cycle, so the average heating is lower.

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