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Need some help making a PCB for a full bridge

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LAN_403

|)4+80!|-|\\/

Tue Jan 02 2018, 12:49PM

Registered Member #61803 Joined: Thu Sept 21 2017, 09:18AM
Location: Bhopal,India
Posts: 34

Hello all!
I'm trying to create a pcb for a full bridge which will eventually drive a DRSSTC
Could you all please provide me with some Pointers and General Do's & Don'ts when it comes to designing such a PCB.
All help is appreciated
Thank you!

Finn Hammer

Tue Jan 02 2018, 02:29PM

Registered Member #205 Joined: Sat Feb 18 2006, 11:59AM
Location: SkÃ¸rping, Denmark
Posts: 741

|)4+80!|-|\\/,

You are welcome.

Cheers, Finn Hammer

E.TexasTesla

Thu Jan 04 2018, 02:27AM

Registered Member #4362 Joined: Sat Jan 21 2012, 03:44AM
Location: Texas
Posts: 98

Well done.

|)4+80!|-|\\/

Thu Jan 04 2018, 01:13PM

Registered Member #61803 Joined: Thu Sept 21 2017, 09:18AM
Location: Bhopal,India
Posts: 34

Just like by watching porn
One doesn't learn how to have sex
By looking at images of full bridges
One can't learn to make one

Perhaps I should've posted images of the Pcb as well

So, well here they are
Please let me know of any possible wrongdoings that I've committed
whilst designing the PCB

1515071615 61803 FT181126 Fool Boad Bottom

the_anomaly

Thu Jan 04 2018, 07:57PM

Registered Member #19 Joined: Thu Feb 02 2006, 03:19PM
Location: Jacksonville, FL
Posts: 168

On the top layer, bottom left corner, the power FET's middle pin does not have copper surrounding the pad. You did this so that the left most leg could be connected to the other power FET on the right. This is bad... Consider rotating the FETs so perhaps you can more evenly cover each pad with copper.

On the bottom layer, top right power FET has extra copper on the (gate?) which the diode is also connected to. The larger the trace the better so this is fine. The other FETs do not have this extra copper... Why? It's not a huge deal but its better to keep uniformity.

Don't forget to run the teardrops ULP. Some of the pads are large so the default values of the ULP will cause it to skip most pads. I would change the default values so all pads get tear dropped.

The bottom layer seems to have more pad to trace clearance than the top layer. Just an observation. Maybe you changed the DRC values in between taking screen shots?

I've found PCB design to be an iterative process. It usually takes a couple tries to come up with a nice design.

Generally:

Vias are not the enemy but the fewer you use the better.

Make traces as large as reasonably possible.

Keep traces as short as possible.

Use copper pours for areas that will have a lot of current flowing.

Fewer traces are better -> leads to simpler design, easier to debug.

Route noisy signals away from sensitive components.

For the future, leave the reference designators ON (Q1, Q2, Q3, C1, C2, C3... ect) so its easier to refer to them when discussing the design.

Think about how much current will be flowing. Many PCB houses will give you 0.5oz Cu or 1oz Cu as the standard so you should request more if you need it. To determine how much you need calculate your desired impedance and temperature rise vs current.

|)4+80!|-|\\/

Sat Jan 06 2018, 06:23AM

Registered Member #61803 Joined: Thu Sept 21 2017, 09:18AM
Location: Bhopal,India
Posts: 34

Thank you for all the feedback

I've redesigned my PCB based on your advice

1515219755 61803 FT181126 Fool Boad Nu Top

alan sailer

Sat Jan 06 2018, 10:59PM

Registered Member #59110 Joined: Mon Apr 11 2016, 04:35PM
Location: Camarillo, California
Posts: 74

the_anomaly,

That was very god of you to help out.

Cheers.

hen918

Sun Jan 07 2018, 05:04PM

Registered Member #11591 Joined: Wed Mar 20 2013, 08:20PM
Location: UK
Posts: 556

There seems like a huge amount of wasted space on that PCB. I tend to spend about half my time when designing a PCB making it smaller to minimise cost and track length. Obviously you have to keep the trace width, but those large areas of copper where little current will flow seem wasted.

I have attached an shot of an H-bridge I designed a while ago for an unregulated switched-mode PSU. As you can see, the MOSFETs are all next to each other for ease of heat-sinking and short traces connect them all.

Weston

Sun Jan 07 2018, 07:25PM

Registered Member #1316 Joined: Thu Feb 14 2008, 03:35AM
Location: Cambridge, MA
Posts: 365

|)4+80!|-|\\/ wrote ...

Thank you for all the feedback

I've redesigned my PCB based on your advice

One of the most important things to optimize in a bridge layout is the leakage inductance of the decoupling capacitor path. Excess leakage inductance causes voltage spikes and ringing which can lead to excess transistor heating / failure.

The amount of leakage inductance can be approximated as the area inside the current path (loop). The path you care about is between the decoupling capacitor for each half bridge segment and the respective MOSFETs. Draw out each path and see how it looks.

For example, for the left half bridge on your board the current path is from the V+ terminal of C1 to Drain of Q3, Source of Q3 to Drain of Q4, Source of Q4 to GND terminal of C1.

If you look at the connection between between the Source of Q4 and GND terminal of C1 you can see that loop is very long. It has to go all the way to the top of the board and around Q3 and the current path is necked down by J3 in the process.

I would spend some time drawing out the loop for each half bridge and trying to optimize it.You also want there to be a nice thick copper path for this entire loop. Strategies to optimize this could include shifting which side you have the gate traces on or shifting the location of C1/ C2.

|)4+80!|-|\\/

Mon Jan 08 2018, 06:59AM

Registered Member #61803 Joined: Thu Sept 21 2017, 09:18AM
Location: Bhopal,India
Posts: 34

Thank you Weston & hen918!!

I've redesigned my PCB based on what y'all've told me

now the size of the PCB is much smaller

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