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My Pulse Skipped DRSSTC &new CPLD driver

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Mr.Black

Fri Mar 24 2017, 04:15AM

Registered Member #3960 Joined: Mon Jun 20 2011, 06:27AM
Location: Wuhan Hubei China
Posts: 33

Very glad to share an experiment with everyone
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A few months ago, in the forum i see some of the posts on the Pulse Skipped DRSSTC.
I'm very interested in it. Find some relevant information, but very lack.
So I consider using CPLD to implement the logic of Pulse Skipped.
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After a clear understanding of the logical relationship, I used Verilog to complete the DEMO validation.
This is an impressive simulation waveform.
Due to the existence of logic competition risk, you can see the rising edge of the int signal, will produce a low level.

He has been able to achieve the functionality of the Pulse Skipped, and does not rely on peripheral analog components.
This version is quite imperfect, but it can achieve some basic functions.
--
I've been working on it for the last three months
--
Now it's RTL as follows

PCB follows it using the Immersion Gold process

It uses a piece of epm240t100c5n to implement logic functions.

My friends gave me a lot of help to finish the design.
I named this drive board "Yunbao", which means "the leopard in the cloud"

â€”â€”
Let's see what it can do

The whole system looks no different from ordinary DRSSTC.
Secondary coil parameters are as follows

I set the supply voltage at 300V ontime to 2.5ms tank current is120A
The arc is very beautiful, and the ribbon is not the same, the arc is relatively coarse.

Using the 1:100 current transformer, the current waveform is measured as follows, and it can be seen that, at the beginning, there is an overshoot that occurs with 100us. I think this is the filter capacitor caused by the comparator delay response
However, it can be observed that, after 100US or so, the "Pulse Skipped" strategy does work properly, and the current is stable at the setpoint.

Continue to raise the voltage up to 420V ontime is 10ms, it can be found that the arc becomes thicker and brighter. It can be painted on the surface of the metal to produce a similar "plasma mass" thing, at this time a shot, the storage capacitor (420v 4700uf) voltage reduced to 280v, which means that nearly 150 joules of energy output.

In this experiment, I use stm8003f3p6 microcontroller timer TIM1/TIM2 work alternately, the hardware interrupt function, int signal is accurate and reliable, through the optical fiber to the "Yunbao", in fact, it can work very well.
I use the instruction format as "_RLD, OTxxx, OFyyy, NUMzzz$".
_RLD, OTxxx, OFyyy, NUMzzz
{
RLD meaning reload parameters
OT meaning is ontime unit is 40us
OF meaning is offtime unit is 8000US
NUM=000, continuous generation of int signal.
NUM = 000, the implementation of a zzz ontime&offtime instruction cycle
}
This int system I still continue to improve the software, after the introduction of a new article details.

So I used the "_RLD, OT250, OF001, NUM001$" to produce a ontime signal for the 10ms of int.

In the 10ms of the time, can be seen from the oscilloscope is obvious, due to the "Pulse Skipped" strategy, the tank current is strictly constant at the set value,

resulting in a large arc arc energy than ordinary dozens of times.

I am very happy with the results of the experiment, and then I plan to use this strategy to achieve "Pulse Skipped QCW"
Hope you can give some good suggestions on this project.
Thanks

Hydron

Sat Mar 25 2017, 01:28PM

Registered Member #30656 Joined: Tue Jul 30 2013, 02:40AM
Location: UK
Posts: 208

Looks really good, especially the PCB!
I am working on a coil with a FPGA + microcontroller for pulse skipping, and will try pulse skipped QCW as well.

Mr.Black

Sun Mar 26 2017, 05:02AM

Registered Member #3960 Joined: Mon Jun 20 2011, 06:27AM
Location: Wuhan Hubei China
Posts: 33

Hydron wrote ...

Looks really good, especially the PCB!
I am working on a coil with a FPGA + microcontroller for pulse skipping, and will try pulse skipped QCW as well.

Thanks
I also plan to use the STM32+EPM240 program to complete my project.
But I have to solve the overshoot problem of int signal
Hope to adjust to upper pole can solve this problem

zzz_julian_zzz

Mon Mar 27 2017, 01:42PM

Registered Member #3964 Joined: Thu Jun 23 2011, 03:23AM
Location: Valenzuela City
Posts: 332

Cool project! Good luck on your pulse skip approach! :)

Mr.Black

Tue Mar 28 2017, 02:02PM

Registered Member #3960 Joined: Mon Jun 20 2011, 06:27AM
Location: Wuhan Hubei China
Posts: 33

zzz_julian_zzz wrote ...

Cool project! Good luck on your pulse skip approach! :)

Thank you for your wishes
For the method of using pulse skip to complete the QCW, I would like to be able to give the voltage comparator positive polarity of a slope voltage signal, so that the tank current changes with the change of the slope voltage signal.
This may allow the output energy to match the growing arc length.
But the difficulty may lie in the fact that the current waveform is not so smooth that it affects the arc straightness

zzz_julian_zzz

Wed Mar 29 2017, 01:47AM

Registered Member #3964 Joined: Thu Jun 23 2011, 03:23AM
Location: Valenzuela City
Posts: 332

Mr.Black wrote ...

zzz_julian_zzz wrote ...

Cool project! Good luck on your pulse skip approach! :)

EXACTLY! I am aware too of the Current envelope of the Pulse Skipped DRSSTC (if you saw some other posts regarding this,

; the current tend to be wiggly and not smooth.. So if you intend QCW SWORD, then this might be your biggest issue.

In my experiments on a bucked QCW, even a slight "deformity" in the current envelope, Spark output will tend to branch - this is my result to "NOT so regulated" Current envelop, to note, this is just minor kinkiness of the waveform..

after few fixes -

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