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Potential Unresolved General Solid State Tesla Issues to Investigate

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Chris_Knight

Sun Feb 07 2016, 10:45PM

Registered Member #58280 Joined: Sat Jan 09 2016, 06:48AM
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Posts: 43

I'm interested in investigating any issue or unresolved problems in Tesla Coils. For example, looking at the effect of secondary width:height ratio on spark length efficiency in relation to power consumption.

Since I'm fairly inexperienced in Tesla Coils, I was wondering if anyone could suggest some potential issues I could investigate. Some unexplained results that you may have come across in your experience, or some interesting trends that you may have noticed.

Mads Barnkob

Mon Feb 08 2016, 09:15AM

Registered Member #1403 Joined: Tue Mar 18 2008, 06:05PM
Location: Denmark, Odense C
Posts: 1968

One of the problems in your proposed width:height ratio issue is that you will be changing many more parameters than just the ratio when trying out different setups.

You would have to work out from a set size of primary coil and coupling, then move your different secondaries in position to achieve the same coupling, but just by positioning the secondary further up or down through primary coil, you have changed the voltage potential distribution on the secondary coil.

I think it is very hard to isolate single parameters in the primary/secondary coil setup to do experiments on, not alone at first determining what kind of setup you will base it on all around that one parameter.

You risk just optimizing the width:height ratio for that particular setup and it might not yield any good results when used in a different setup.

From what we have seen on QCW, low/high impedance coils and long on-time coils, the best optimization lies in voltage wave form shaping or dumping more power over longer time into the circuit.

Chris_Knight

Mon Feb 08 2016, 09:59AM

Registered Member #58280 Joined: Sat Jan 09 2016, 06:48AM
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Hm, you're right about the secondary primary variable isolation issue.

Mads, can you elaborate on your last point?

Mads Barnkob

Mon Feb 08 2016, 10:24AM

Registered Member #1403 Joined: Tue Mar 18 2008, 06:05PM
Location: Denmark, Odense C
Posts: 1968

Chris_Knight wrote ...

Mads, can you elaborate on your last point?

I assume you wanted to find something to optimize for longer spark length. The DRSSTC in itself with a "standard" built running 120BPS, 100-200uS on-time, at some 1000Apeak from rectified mains perform just about the same when tuned good, from a various of different builds.

Where we really see extraordinary spark lengths are in the QCW coils where you control the DC bus voltage very tightly or long on-time coils where its a large amount of power being transfered over a much longer on-time period, into several miliseconds.

F.ex.

I just think there is more improvement to see in studying dc bus voltage shaping than on primary/secondary coil setup. There are quite a lot of good threads put together in the DRSSTC sticky thread with models and theory, combine some of all that knowledge and go from there :) It is without a doubt a large undertaking to first understand it all and then develop further on it.

Sulaiman

Mon Feb 08 2016, 01:29PM

Registered Member #162 Joined: Mon Feb 13 2006, 10:25AM
Location: United Kingdom
Posts: 3140

One thing that may be interesting may be to have a series of secondaries,
each of the same dimensions but different number of turns,
either the primary capacitor value or preferably the primary inductance tap will need to be adjusted to match.

One thing that I promised myself was to one day wind two identical secondaries except one wound clockwise and one anti-clockwise
I suspect that the tendency to arc down to the strike rail / primary is influenced by this, for a given primary.
i.e. is it best to wind the primary and secondary in the same direction or opposite ?
I've not done it yet !

Sigurthr

Tue Feb 09 2016, 12:35AM

Registered Member #4463 Joined: Wed Apr 18 2012, 08:08AM
Location: MI's Upper Peninsula
Posts: 597

In the field of CW-SSTCs the only real "unsolved" thing is the search for a better (than the craptastic 4046pll) PLL or VCO for FM audio modulation and f0 tracking. The 4046 isn't really up to the task despite its prevalence for the role.

We have some *really* advanced members replacing the 4046's PLL PhaseComparator with discrete and logic chips, but the build scheme is pretty builder unfriendly if you're not used to working with those types of topologies.

I've done some experimentation with the LTC6990 VCO, which is a very easy to use (few-external components needed) monolithic wideband VCO. Unfortunately it only comes in SOT-223 which is not very user friendly. Being that it's just a VCO it's fine for tuned SSTCs but isn't self-resonant or resonant tracking.

If there was a simple PLL which didn't suffer the from the failings and pitfalls that plagues the 4046, and allowed for easy FM modulation and wideband frequency selection like the 6990 we'd (the CW crowd) be very happy.

Chris_Knight

Tue Feb 09 2016, 12:41AM

Registered Member #58280 Joined: Sat Jan 09 2016, 06:48AM
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Posts: 43

Maybe PLL via digital FPGA control would work, though, I'm not familiar enough with FPGAs to know if and how.

I think I came up with a simple and doable experiment. I would look at primary secondary coupling in relation to performance; perhaps asking if there is a "magic" value constant that will provide across the board good performance for SSTCs, regardless of secondary length or frequency. What kind of work has been done here?

Mads Barnkob

Tue Feb 09 2016, 07:48AM

Registered Member #1403 Joined: Tue Mar 18 2008, 06:05PM
Location: Denmark, Odense C
Posts: 1968

Chris_Knight wrote ...

Maybe PLL via digital FPGA control would work, though, I'm not familiar enough with FPGAs to know if and how.

I think I came up with a simple and doable experiment. I would look at primary secondary coupling in relation to performance; perhaps asking if there is a "magic" value constant that will provide across the board good performance for SSTCs, regardless of secondary length or frequency. What kind of work has been done here?

As Siguthr points out, there is a builder friendliness factor in this too, FPGA solutions will be limited to a narrow band of people, whereas everything in DIP is widely rebuilt/copied/elaborated on, that is much harder with software without a proper community driven development of said software on something like github.

My experience from SSTCs is that the best coupling would be 1 :) I got better results the more layers of insulation I removed and that only last as long as to the first flashover. The lower peak currents does not make it necessary with so much distance as in DRSSTCs.

Chris_Knight

Tue Feb 09 2016, 08:19AM

Registered Member #58280 Joined: Sat Jan 09 2016, 06:48AM
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Posts: 43

Mads, I thought that the general sweet spot for coupling was between 0.2 and 0.5. At least that's what I've read concerning SGTCs.

So do you think there is anything of interest to pursue in this area? I feel like there's something there, something about number of turns, diameter of primary, comparing theoretical simulation to experimental values...

Mads Barnkob

Tue Feb 09 2016, 11:44AM

Registered Member #1403 Joined: Tue Mar 18 2008, 06:05PM
Location: Denmark, Odense C
Posts: 1968

I would go with sulaimans suggestion of using a DRSSTC with flat primary coil, maybe fixed/or tapable MMC and then try out secondaries of same dimension with different number of turns/thickness and also larger and larger topload as the Fres of the secondary goes up.

If you could maintain the same primary circuit frequency, coupling to secondary and only vary secondary/topload, that might be isolated enough to examine that at a certain frequency, now repeat that for 100, 200, 300, 400 and 500 Khz :)

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