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Method for determining maximum acceptible hard switching frequency for MOSFETS/IGBTs

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Sigurthr

Sat Dec 21 2013, 10:37AM

Registered Member #4463 Joined: Wed Apr 18 2012, 08:08AM
Location: MI's Upper Peninsula
Posts: 597

Hey everyone!

So I was shopping around for some fets/IGBTs today and while going about my business through a pile of datasheets it dawned on me that perhaps I am not going about the proper method to determine the maximum acceptable switching frequency. Now, I know that there isn't really a true maximum; you just incur more loss as you spend more percentage of your half cycle in the linear region, and your gate drive has to deliver more current to charge and discharge the gate capacitance as frequency increases. But there has to be a conventionally accepted range, if not limit, for what is and isn't too fast, or perhaps for the percentage of half cycle time spent switching, right? Keep in mind this is for regular old hard switching, no ZCS, no ZVS, no Class-E, and so on.

Here is what I had been doing:

Take the FHG50N3 IGBT from FairchildSemi:
Turn on delay: 20nS
rise: 15nS
turn off delay: 135nS
fall: 12nS

I would add all of these delays together to get 182nS total switching time. Then assume (a largely arbitrary) limit of 10% of the half-cycle to be spent switching. So, 182nS x 10 = 1820ns, or 1.82uS. So, I'd assume 1.82uS to be the shortest acceptable ON pulse width. That works out to 2(1,000,000 / 1.82) = 1.098MHz assuming 50% duty cycle.

This all of course leaves out the thermal calculations, which I only recently discovered (but have not tried out) the method and math for. Obviously if you liquid or cryo cool the switch then you're just at the mercy of the junction to case thermal resistance and the gate drive capability. I've always taken a practical (read: trial and error) approach to the thermal management side of things; try it at desired frequency, if it gets too hot add a bigger heatsink. If it is still to hot; add a fan. If it is still to hot; parallel up two switches to share the load.

So, if there isn't a set and or accepted method for determining acceptable frequency threshold, how do YOU determine if a switch is too slow for your project's needs?

Carbon_Rod

Sat Dec 21 2013, 11:33AM

Registered Member #65 Joined: Thu Feb 09 2006, 06:43AM
Location:
Posts: 1155

Look at the app notes:

Sigurthr

Sun Dec 22 2013, 04:01AM

Registered Member #4463 Joined: Wed Apr 18 2012, 08:08AM
Location: MI's Upper Peninsula
Posts: 597

Thanks for the article! While some of it is certainly over my head, I did manage to learn a lot from it.

Though, one thing that seems contradictory is the use of large value gate resistances when adapting a circuit from MOSFET to IGBT use. I didn't catch why that was being done, either it wasn't mentioned or explained, or I just missed it. It seems to me you would want to allow as much current as you can to flow into and out of the gates to achieve fast rising and falling edges. It did show the use of an in series but parallel to Rg reverse biased diode for fast discharging of the gates, which makes perfect sense if you need to heavily dampen parasitic oscillations on the gate by adding gate resistance. Still, from our SSTC/DRSSTC work we've seen a handful of ohms is plenty to dampen parasitic oscillations on the gate, and I think most of us push the operating frequency far beyond what is used in the SMPS industry.

In the end the article just says (paraphrasing): "the issue of part selection is very complex and mostly comes down to your cooling solution and space/budget restraints". While obviously true, it isn't very helpful at establishing a benchmark, guestimation, or baseline for what kind of speed a particular switch should or should not be pushed to.

IamSmooth

Sun Dec 22 2013, 04:27AM

Registered Member #190 Joined: Fri Feb 17 2006, 12:00AM
Location:
Posts: 1567

Gate resistance is added as a means to help minimize ringing. Ringing (oscillations) would result in high frequency spikes that will destroy the chip.

Sigurthr

Sun Dec 22 2013, 06:21AM

Registered Member #4463 Joined: Wed Apr 18 2012, 08:08AM
Location: MI's Upper Peninsula
Posts: 597

Right, it wasn't the issue of having a Rg, but rather having such a high value, that eluded me. You're limited in how much voltage you can apply to a gate before reaching Vgs breakdown and destroying the chip, so having 100ohms for Rg at a suggest Vgs of 10V you're limiting the gate charge current to only 100mA. My point is that the article states a "desired dI/dT" for the gate and designs a Rg around that, but it doesn't state where it gets the desired dI/dT from.

Gate drive current requirement can be calculated with:
I = (C * V) / t
where:
C = input capacitance
V = Vgs dV
t = time voltage is applied to the gate

Let's try an example: CM300 @ 50KHz.
1/50000 = 2e-5
2e-5 / 2 = 1e-5 for a half cycle
I= (83e-9 * 10) / 1e-5
I= 83mA

now lets try at 100KHz:
t= (1/100000)/2 = 5e-6
I= (83e-9 * 10) / 5e-6
I= 166mA

Now lets try my limit for a CM300:
the CM300 has 1.35uS total switching time, so assuming the 10% switching time allowance the shortest pulse width ON time is 13.5uS, which at 50% duty cycle CW is 148KHz.
2(1000000/13.5) = 148148Hz

t= (1/148000)/2 = 3.37e-6
I= (83e-9 * 10) / 3.37e-6
I= 246mA
R = V/I
R= 10 / .246
Rgmax= 40Ohms

I can't apply the same math they used in the article because I have no idea what a "desired dI/dT" for a CM300 gate should be. My point still stands though; a desired gate dI/dT determines your Rg, which limits the Igs, which limits how fast you charge your gate capacitance, which limits your switching frequency (thermal aspects aside), so by limiting gate dI/dT you're declaring a maximum switching frequency.

Edit: reread the article and it says:

wrote ...
Decreasing the drive source resistance will increase the
IGBT or MOSFET turn-on di/dt and decrease the Eon loss.
The tradeoff is between Eon losses and EMI, since the higher
di/dt will result in increased voltage spikes and radiated and
conducted EMI.

So this means they're using radiated and conducted EMI as a limiter for switching frequency? That has nothing to do with the actual switching device itself though!

Kizmo

Sun Dec 22 2013, 10:55AM

Registered Member #599 Joined: Thu Mar 22 2007, 07:40PM
Location: Northern Finland, Rovaniemi
Posts: 624

Another thing with brick type transistors is the module internal inductance (usually in range of 10-100nH depending the size of the transistor) It will limit your usable rise and fall times and there is nothing you can do about it.

For example it its perfectly possible to build a gate driver that is capable of slamming the CM600 gate from 0V to 24V in less than 200ns and have very little or no ringing at all on the gate waveform. But then you may have horrendous ringing and voltage spikes at the collector-emitter waveform due to the module internal inductance ringing with part of the bus capacitance or bus decoupling capacitors.

This is where the EMI problems come from. You dont want 10s or 100s of MHz ringing that can radiate everywhere :)

Sigurthr

Mon Dec 23 2013, 09:02PM

Registered Member #4463 Joined: Wed Apr 18 2012, 08:08AM
Location: MI's Upper Peninsula
Posts: 597

Ah, I see, thanks! Is there no way to reduce the Vds / Vce ringing with snubbers and such?

Dr. Dark Current

Tue Dec 24 2013, 12:23AM

Registered Member #152 Joined: Sun Feb 12 2006, 03:36PM
Location: Czech Rep.
Posts: 3384

Sorry no time to read the whole thread, but IGBT losses are calculated based on the turn-on / turn-off energies manufacturer provides in the data sheet. Conduction losses are clear. You can then calculate the maximum frequency based on your case and junction temperatures (either steady state, or if pulsed, the transient thermal response must be used)

Kizmo

Tue Dec 24 2013, 08:28AM

Registered Member #599 Joined: Thu Mar 22 2007, 07:40PM
Location: Northern Finland, Rovaniemi
Posts: 624

Sigurthr wrote ...

Ah, I see, thanks! Is there no way to reduce the Vds / Vce ringing with snubbers and such?

In this case snubbers will be efficient and effective only if you can place them right at the igbt chips (inside of the brick...)

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