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Negative gate voltage for IGBT bricks

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Dr. Dark Current

Wed Jan 09 2013, 07:33PM

Registered Member #152 Joined: Sun Feb 12 2006, 03:36PM
Location: Czech Rep.
Posts: 3384

Hi, I'm facing a problem with generating negative gate voltage on an IGBT gate during the dead-time, should the turn-off gate voltage always be negative or can I get away with 0 volts?

Sulaiman

Wed Jan 09 2013, 08:29PM

Registered Member #162 Joined: Mon Feb 13 2006, 10:25AM
Location: United Kingdom
Posts: 3140

afaik it is common to use 0V as the OFF voltage for an IGBT gate.
The negative gate-emitter voltage is mainly to speed up the IGBT turn off
which is quite critical for high-speed (sstc) switching loss/heat.
I'd GUESS that the benefit of negative gate voltage outweighs the extra cost/effort of providing it.
Industrially almost always a UC3xxx type inverter.
For super-simple these are quite common

Dr. Dark Current

Wed Jan 09 2013, 10:57PM

Registered Member #152 Joined: Sun Feb 12 2006, 03:36PM
Location: Czech Rep.
Posts: 3384

Well, a power electronics engineer told me that it is safer to use negative voltage for turn-off, the transistor is then less prone to latching etc. But I don't know if that's true...

Ben Solon

Thu Jan 10 2013, 12:29AM

Registered Member #3900 Joined: Thu May 19 2011, 08:28PM
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Posts: 600

really, it just decreases shoot-through. with the rising and falling edges not as close to square as you may like, their cross will be at 0v if you have a symmetrical bipolar supply. if not, it still lowers the gate voltage at the shoot-through, minimizing harmful effects. when the gate voltage is at 0-24v, the cross would be at 12 if the gates had any overlap in on times. i'd recommend it simply because with two separate solid state gate drives, there will be differences that result in less than perfect switching(as opposed to a gdt where it's not possible to have both windings high at the same time if the're inverted).

lightlinked

Thu Jan 10 2013, 12:47AM

Registered Member #2087 Joined: Tue Apr 21 2009, 08:32AM
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if your not using a gdt there is the risk of shoot through using separate drivers. is there an advantage to dead time vs. just switching early in a drsstc?

teravolt

Fri Jan 11 2013, 02:58AM

Registered Member #195 Joined: Fri Feb 17 2006, 08:27PM
Location: Berkeley, ca.
Posts: 1111

I always use 0-20v and don't have any problems. Direct drivers generaly has delay plus the delay in the controle electronics in front of them thats why phase leeding is used to switch early around zero cross. Alot of IGBT's have such a bad rise time that the turn off time and turn on time of the other device intersects cousing shoot through. I add about 100 to 200ns between each switching device with a one-shot in my electronics. I've also seen RC networks and TTL to make dead time. I am not to shure if it is pausible to add dead time to a GDT. Well thats how I understand it hope it helps.

GeordieBoy

Mon Jan 21 2013, 02:32PM

Registered Member #1232 Joined: Wed Jan 16 2008, 10:53PM
Location: Doon tha Toon!
Posts: 881

Actually the negative gate bias on IGBTs and MOSFETs when they're meant to be off is typically to reduce the chances of something called "dv/dt induced turn on".

This is where the turning on of an opposite device in a bridge-leg (say the top IGBT) causes the voltage impressed across this device (say the bottom IGBT) to increase very rapidly indeed. (Engineers call this high dv/dt - A high rate of change of voltage.) Because of an IGBT device's intrinsic collector-gate capacitance this high rate of change of collector voltage can result in a voltage developing on the gate. If this gate-emitter voltage reaches the threshold voltage for the device then the channel will become enhanced and it will start to turn on. This situation is clearly the last thing that you want a power-electronics switch to do when you have just started to turn on the opposing device!!!

The higher the turn-on dv/dt is in the circuit the more current flows through the collector-gate capacitance and the higher the gate voltage peaks.

Biasing the gate negative with respect to an IGBT's emitter (or MOSFET's source) increases the immunity to dv/dt induced turn-on caused by the Miller capacitance when the device is meant to remain firmly switched off. Example...

A typical MOSFET might have a Vgs(th) value of about 3 volts, and have it's gate driven via a 47R damping resistor. Consider that you apply 0 volts of Vgs when the device is meant to be off (essentially tie the gate to the source via the 47R resistor.) It only takes 64mA of current through the drain-gate capacitance to make the gate voltage rise above 3 volts and the device to start to turn on. (You could work out what rate-of-rise of drain voltage would risk causing this to happen by looking at the devices Cdg figure.) _However_ if you bias the gate at -15 volts with respect to the source when the device is meant to be off, then it requires a much greater 383mA of displacement current through the drain-gate capacitance for the gate to come up to the threshold voltage for conduction. That's six times greater immunity to dv/dt induced turn-on, meaning that you can turn on all your switches that much quicker (to minimise linear-area switching losses) without having to worry about dv/dt induced shoot-through.

I hope this explanation helps,

-Richie Burnett,

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