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Registered Member #2922
Joined: Sun Jun 13 2010, 12:08AM
Location:
Posts: 226
I was projecting a new driver for my future big DRSSTC, and junt now I noticed that the normal flip-flop synchronizer with clock attached th the feedback input will only reset the driver enable when tke feedback goes high, so it will have half chance of wait more than 1 cycle to turn off the driver when OCD trips and will not turn off at the end of the current cycle.
Maybe isn't better make some syncronizer that reset on the falling and the rising edge of the cycle? I think it can save some igbts, because it will prevent one more cycle off over-current.
Registered Member #30
Joined: Fri Feb 03 2006, 10:52AM
Location: Glasgow, Scotland
Posts: 6706
If you start switching in increments of half cycles, then it becomes possible to have a DC component in the gate drive waveform. I don't like the thought of that, so I've always used increments of one cycle.
Registered Member #570
Joined: Wed Mar 07 2007, 03:41PM
Location: Winchester Uk
Posts: 42
I was thinking the same and was going to use an XOR frequency doubler in the clock feedback used to do the reset.
If it does stop mid cycle would the core recover before the next burst I wonder? I had not thought about the DC.
Perhaps in a pulsed system there is some DC anyway from the coupling capacitor charging or discharging when it starts and stops.
So far I have only run CW, I have yet to get to a pulsed system so don't know the answer. One thing is for sure, the present system works very well, whether the extra complexity is worth it who knows.
Registered Member #2922
Joined: Sun Jun 13 2010, 12:08AM
Location:
Posts: 226
I was thinking in the XOR doubler too.. But only now I notice the possibility of DC components in the gate drivers.. But if I have a bleeder resistor at the output cap of the gate driver, it will drain all the DC componente that can be in the cap.
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