If you need assistance, please send an email to forum at 4hv dot org. To ensure your email is not marked as spam, please include the phrase "4hv help" in the subject line. You can also find assistance via IRC, at irc.shadowworld.net, room #hvcomm.
Support 4hv.org!
Donate:
4hv.org is hosted on a dedicated server. Unfortunately, this server costs and we rely on the help of site members to keep 4hv.org running. Please consider donating. We will place your name on the thanks list and you'll be helping to keep 4hv.org alive and free for everyone. Members whose names appear in red bold have donated recently. Green bold denotes those who have recently donated to keep the server carbon neutral.
Special Thanks To:
Aaron Holmes
Aaron Wheeler
Adam Horden
Alan Scrimgeour
Andre
Andrew Haynes
Anonymous000
asabase
Austin Weil
barney
Barry
Bert Hickman
Bill Kukowski
Blitzorn
Brandon Paradelas
Bruce Bowling
BubeeMike
Byong Park
Cesiumsponge
Chris F.
Chris Hooper
Corey Worthington
Derek Woodroffe
Dalus
Dan Strother
Daniel Davis
Daniel Uhrenholt
datasheetarchive
Dave Billington
Dave Marshall
David F.
Dennis Rogers
drelectrix
Dr. John Gudenas
Dr. Spark
E.TexasTesla
eastvoltresearch
Eirik Taylor
Erik Dyakov
Erlend^SE
Finn Hammer
Firebug24k
GalliumMan
Gary Peterson
George Slade
GhostNull
Gordon Mcknight
Graham Armitage
Grant
GreySoul
Henry H
IamSmooth
In memory of Leo Powning
Jacob Cash
James Howells
James Pawson
Jeff Greenfield
Jeff Thomas
Jesse Frost
Jim Mitchell
jlr134
Joe Mastroianni
John Forcina
John Oberg
John Willcutt
Jon Newcomb
klugesmith
Leslie Wright
Lutz Hoffman
Mads Barnkob
Martin King
Mats Karlsson
Matt Gibson
Matthew Guidry
mbd
Michael D'Angelo
Mikkel
mileswaldron
mister_rf
Neil Foster
Nick de Smith
Nick Soroka
nicklenorp
Nik
Norman Stanley
Patrick Coleman
Paul Brodie
Paul Jordan
Paul Montgomery
Ped
Peter Krogen
Peter Terren
PhilGood
Richard Feldman
Robert Bush
Royce Bailey
Scott Fusare
Scott Newman
smiffy
Stella
Steven Busic
Steve Conner
Steve Jones
Steve Ward
Sulaiman
Thomas Coyle
Thomas A. Wallace
Thomas W
Timo
Torch
Ulf Jonsson
vasil
Vaxian
vladi mazzilli
wastehl
Weston
William Kim
William N.
William Stehl
Wesley Venis
The aforementioned have contributed financially to the continuing triumph of 4hv.org. They are deserving of my most heartfelt thanks.
Registered Member #27
Joined: Fri Feb 03 2006, 02:20AM
Location: Hyperborea
Posts: 2058
My understanding is that it's still a single CPU, but with extra circuitry to let it do fast hardware context switches between two threads.
There is no context switching, it is two separate instruction decoders that feed the same ALUs. Since the ALUs were out of order anyway it did not take a lot of extra logic since they already had the capability to run several contexts at once and separate them at a later stage.
Some of the ALUs run at twice the frequency of the rest of the CPU and it is unusual for a program to use all of them at once. That means that there is always a lot of free slots.
If you run two programs at once, one with integer code and one with MMX code you will get a huge speed increase. If you run two programs that use the exact same instructions but different memory areas then the increase will be smaller because there will be less free instruction slots and they will reduce the efficiency of the cache since twice as much data needs to fit in it.
I divide my program into an interrupt service routine with all the signal processing stuff, and a main loop that does everything else, and swap between them hundreds to thousands of times per second. I guess it's ghetto hyperthreading.
I did that on the ARM a decade or two ago at slightly lower frequency, it can do magic in only 25 000 transistors.
Registered Member #65
Joined: Thu Feb 09 2006, 06:43AM
Location:
Posts: 1155
IIRC the ARM thumbnail mode was designed to provide memory space saving and legacy compatibility features.
As for the differences in high-end chips and cheap consumer chips -- the dirty little secret is often related to replacing expensive hardware with microcode structures (which can chop your instruction cycle efficiency by n-operations.) Usually a manufacture will not advertise this part as a feature of a budget system. =o] For example if you theoretically purchased a 3GHz system that takes 157 instruction cycles to do whatever and use the emulated instruction often -- then actually you purchased the equivalent of a 19MHz system that has a the hardware instruction. It is usually not quite this bad as most code will never make use of these non-standard instructions.
Therefore on rare occasion an optimizing compiler can un-optimize code on some CPUs. Notably, there was some corporate mudslinging related to AMD brand chips and a certain software manufacturer.
This site is powered by e107, which is released under the GNU GPL License. All work on this site, except where otherwise noted, is licensed under a Creative Commons Attribution-ShareAlike 2.5 License. By submitting any information to this site, you agree that anything submitted will be so licensed. Please read our Disclaimer and Policies page for information on your rights and responsibilities regarding this site.
MySQL or Oracle?
