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Registered Member #152
Joined: Sun Feb 12 2006, 03:36PM
Location: Czech Rep.
Posts: 3384
Patrick, if you want to calculate the dissipation in the transistors then you need to measure the output current waveform of the bridge and then calculate its RMS value. P=I^2*Rdson. Increase of Rdson with temperature must be taken into account, with ~100-120°C die temperature, the Rdson is usually as high as 200% of the original value.
Just as an extreme example, take the bridge driving an inductor (a leakage-limited transformer into a short-circuit, for example), if you measured the average input current to the bridge it would be close to 0 (actually covering just the losses) but the bridge output current would be large.
Registered Member #3943
Joined: Sun Jun 12 2011, 05:24PM
Location: The Shire, UK
Posts: 552
Back now finally, college got in the way.
I ended up building another one based around a large heatsink I had.
I have got mixed results from it. On one hand I seem to require less power for the same size arc (although this is a plasma speaker so arc length is not too important beyond an inch or two).
Thing is that heatsink still gets pretty warm after a few minutes
The only thing that seemed to help was putting a capacitor and resistor in parallel with the primary coil. I used a 270nF and a 560 ohm resistor, not sure if that is too big or too small but it also seemed to make the audio in the arc slightly clearer.
I also tried putting a DC blocking capacitor in series (1uF) with the primary coil but that stops any output from the transformer. When I viewed the gate to source waveforms on my scope they appeared to be slower than when I had it made on my breadboard! odd...
Gate drive transformer is type 77 materiel from easternvoltageresearch and I have 3x 13 turns trifilar using bell wire.
Driver runs on 15v and the bridge is 24-36v depending on how much power I want to give it, ill add a few more turns to the primary coil at some point so I can use 36v and less current for the same power (again I seem to be getting bigger arcs at lower powers than my last setup)
Also can anyone give me any tips/pointers as to the layout of my power section? I mean should I add more lengths of bare copper and add lots of solder or will that increase stray inductance? (I ran out of solder so that is why the joints around the FET's are poor).
Should I add a capacitor directly across the top FET's drain and bottom FET's source pin (Power and ground)? As my main 36v rail cap is quite far away since I ran out of space but I can easily add an MKP cap on the underside of the board.
Primary coil connects here via a 10cm long tightly twisted pair.
Finally, should I connect my power and driver grounds together? As I had an idea of connecting the LOPTs/flybacks return pin to the power section ground along with the heatsink and actually using the heatsink as a return electrode.
Its probably a stupid idea I know but it seems a bit safer having at-least one end of the HV connected to circuit ground. The flyback transformer is actually an AC one now, well it started life as a DC one but the internal diodes have failed from over voltage and I can measure the internal secondary winding resistance via my multimeter in both directions.
Registered Member #3215
Joined: Sun Sept 19 2010, 08:42PM
Location:
Posts: 780
you should have a single ground plane, a central power ground point where all and every power ground joins, and then you have to connect the power ground point to the ground plane, close to the filtering caps
Registered Member #3943
Joined: Sun Jun 12 2011, 05:24PM
Location: The Shire, UK
Posts: 552
@Shrad Don't you need a PCB to do that?
I have remade my power sections layout and taken more waveforms.
Is this better? (I know its ugly and there is flux everywhere!).
Gate drive waveform with no voltage on the bridge 5v/div 200ns/div
Gate drive waveform with 22v on the bridge and a 150R power resistor as a load (that was using some used 9v battery's in series). So I would imagine with an inductive load drawing a few amps it will be even worse. 5v/div 200ns/div
This also appears when there no load on the bridge, just voltage being applied to the bridge. Could this be the MOSFET's miller effect?
Vds with the 3 9v battery's as the power source, 150r resistor load. 5v/div 10us/div
Now I am probably wrong here, but that looks like it happens at turn off indicating the body diode of the FET is ringing? Again that is using a 150r wire-wound resistor as the load.
Same as above but with a 470nF film capacitor across the upper FET's drain and lower FET's source pins (ie supply rails). 5v/div 10us/div
Does this look ok and what other improvements can I make to the power sections layout? Should I make the tracks even wider? I don't really know what makes for a "good" low inductance layout besides having things as physically close as possible.
Also I realise with an inductive load on the bridge there will be more ringing from the windings leakage inductance, so if I was to use RC snubbers across the DS of each FET what value should the capacitor and resistor be for 36v operation? or will just using an RC snubber across the primary coil be enough?
Registered Member #3943
Joined: Sun Jun 12 2011, 05:24PM
Location: The Shire, UK
Posts: 552
Daedronus wrote ...
you can try to slow down the turn on, while keeping the turn off, with R in parallel with a diode.
This will reduce a bit the turn on spike.
IMHO the waveforms look quite good.
Hmm well I guess I will have to try putting a heavier load on the bridge and checking again, since that was only with a very small load and half dead 9v battery's.
I thought that it was at the FET turn off when the spikes occur, since the voltage across the FET only appears when the FET is turned off.
I got some more waveforms when powering a 12v PC fan drawing 200mA, 36v(ish) on the bridge. That was giving me about 18v when I rectified the bridges output and added a capacitor. Then I put a 12v regulator between the fan and cap.
So that is around 38v on the bridge since my battery's are fully charged drawing a very low current (60-ish milli-amps).
Top FET Vds 20v/div 5us/div
Bottom FET Vds 20v/div 5us/div I also had my probe set to 10x here, but am not sure if I really needed to.
I am curious, is this difference in ringing amplitude becuase of the miller effect or is this also layout related?
Perhaps the top FET is effected by miller capacitance more or some other reason?
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