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Routing differential LVDS signals

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rp181

Wed Oct 19 2011, 02:12AM

Registered Member #1062 Joined: Tue Oct 16 2007, 02:01AM
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Posts: 1529

I am about to route some LVDS lines, and I had a couple of questions.
The impedance is supposed to be kept at 100ohms. Do I just use the trace impedance, or do I put a 100 ohm resistor across the lines on the receiving end? Do I put the resistors on the transmitting end?
What I am planning is using these:

to find a good trace width and spacing, and connecting them directly to the connector while keeping trace length and spacing constant. For the receiver, I will do the same but put a 100 ohm resistor from the + line to the - line.

2Spoons

Wed Oct 19 2011, 02:47AM

Registered Member #2939 Joined: Fri Jun 25 2010, 04:25AM
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Whether or not you need to add resistors depends on your driver and receiver - you will need to check the data sheets. Line termination is necessary, but may already be built in.

rp181

Wed Oct 19 2011, 03:18AM

Registered Member #1062 Joined: Tue Oct 16 2007, 02:01AM
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So I got rid of the receivers. Yep, I got it! Thanks.

Carbon_Rod

Wed Oct 19 2011, 05:07AM

Registered Member #65 Joined: Thu Feb 09 2006, 06:43AM
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Most chips use adjacent i/o pins even when emulating external LVDS interfaces.

TI Handbook:

Multi-point notes:

Xilinx notes:

More notes:

Numerous fpgas have documented support for LVDS ports built-in.

$37 with RAM

EP1C6Q240C8N:

rp181

Wed Oct 19 2011, 10:28PM

Registered Member #1062 Joined: Tue Oct 16 2007, 02:01AM
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How does this look? I don't know how I am supposed to keep them the same distance if I need to keep them the same length. I did a trombone kind of thing to keep the same length.

2Spoons

Thu Oct 20 2011, 03:19AM

Registered Member #2939 Joined: Fri Jun 25 2010, 04:25AM
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I would say you've just thrown away the impedance matching. If you look at routing on motherboards the length matching wriggles are usually quite small, and perpendicular to the routing direction. To be honest, my gut feel is that 2mm(?) of length error wont matter, but putting in what are effectively PCB inductors could cause trouble. I don't suppose you are allowed to change the pinout on that connector?

Dr. Slack

Thu Oct 20 2011, 07:16AM

Registered Member #72 Joined: Thu Feb 09 2006, 08:29AM
Location: UK St. Albans
Posts: 1659

If you are going to run them as a pair, wiggle them as a pair.

If you are going to wiggle them independantly, run them as 2 independant 50 ohm lines rather than as one balanced 100 ohm line, and keep them the same length. This is the way you'd shift LVDS from one chassis to another.

The lines don't have to be, and never will be even if you try, the same length. You are allowed a difference tolerance. You can work out the size of the tolerance knowing your transmitter rise-time. You want the two transitions arriving at the recevier to overlap by an absolute minimum of 50%. Consider the case where they don't overlap at all - the differential voltage goes from -100% to 0% as one trnanstion arrives, then from 0% to +100% as the other one arrives - the worst possible case, as the voltage dwells for a long time at the receiver's mid-way threshhold. 50% overlap assures that the transition from the first one has not started, by the time the second arrives and increases the differential slew rate seen at the recevier.

So, if you know your transmitter risetime, the largest time or length difference you should accept between paths is half the length. If for the sake of argument, you have a 400Mbps transmitter, which might have a risetime of period/8 = 0.3nS. You would then want a path skew of less than 0.15nS.

Now the speed of light is 1ft / nS (one of the handiest rules of thumb a PCB designer has). Therefore 0.15nS is 1.8" in air, so about 1" on a typical circuit board trace. Now we see why HDMI and SATA started at 1.5Gb/s and have only recently moved to 3Gb/s, keeping paths matched gets ihncreasingly difficult as you go up in rate

rp181

Thu Oct 20 2011, 12:13PM

Registered Member #1062 Joined: Tue Oct 16 2007, 02:01AM
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Aah, ok. Thank you! 50% would be 4.5" in my case, which is significantly smaller then my board. I will reroute that!

MRacerxdl

Thu Oct 20 2011, 01:45PM

Registered Member #989 Joined: Sat Sept 08 2007, 02:15AM
Location: SÃ£o Paulo, Brazil
Posts: 476

A long time ago I made one TFT LCD Controller with this FPGA Board:

I used twisted pairs wire soldered to LCD and never had any problems. I also made a DVI Connection.

If the sample rate is low, I dont think you really need to care about it. I used a 1024x768 @ 60Hz with 18 Bit Interface that gave me 849MBps Sample rate at total, but that was divided by three LVDS lines so about 283Mbps per line.

I tryed higher clocks, but my FPGA cant support higher clocks.

Here is a video: (LCD + DVI Interface)

EDIT: Also, it seens to you are using a DVI Interface, you know that DVI isnt LVDS right? Its TMDS. Its a other concept of Differetial Signal.

rp181

Thu Oct 20 2011, 09:03PM

Registered Member #1062 Joined: Tue Oct 16 2007, 02:01AM
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Posts: 1529

Hey,
I am using CameraLink. It is 5LVDS Data + a Clock. Could someone verify these for 100 ohm differential impedance?
1 oz copper
8.4mil spacing from a ground plane (6 layer PCB)
12 mil trace
7.68 mil spacing
Relative permetivity of 4.5 (reasonable figure for prepreg?)
I am getting 113ohm Differential Z.

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