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The gate drivers are tc4420cpa with isolated power supply and 10Mbit opto couplers, and with 6 Ohm resistors to the mosfet gate. I can try to load the bridge with something else...I will try to do that tomorrow..
Registered Member #2431
Joined: Tue Oct 13 2009, 09:47PM
Location: Chico, CA. USA
Posts: 5639
you do realize that the cap labeld C1 shuold be small right? otherwise you wont have pulse by pulse limit, youll have average CL, i think your haveing a Leading edge blanking problem, thats why you see the first rise on your CT, then the rise for the rest of the pulse. your comp in and Vfb in need tobe checked too.
Sorry, for the confusion, I was drowning the schematic from memory. R1 is 1Ohm and C1 is 0.01micro, so it should be OK. The current waveforms, blue in the first movie above is after the RC filter.
I tested the whole thing with a resistive load today
Primary voltage (with resistive load), primary current, open loop, I don't think this kind of waveform can be used for pulse by pulse, since it's square. I probably need some inductance....
The "thing"
Current transformer
Load
PWM IC Board and the PWM divider, takes 1 PWM signal and makes 2 at half the frequency and posing phases
Registered Member #2431
Joined: Tue Oct 13 2009, 09:47PM
Location: Chico, CA. USA
Posts: 5639
Im fearful that your problem is a layout problem, but maybe not. Maybe if you described the problem again in detail, i can help you, im already re-reading this whole thread.
Layout is definitely not too good, but, the power section I think is ok, loats of capacitance right next to the fets, and, short and thick traces. I'm not sure if the noise on the gate is withing acceptable limits, it's perfectly clear while the main power is disconnected, but I do get those nasty spikes while the main power to the fets is on, but there doesn't seem to be any superfluous tun on of the mosfets.
The best example of what my problem is can be seen in the first movie in the first post. There you can see the gate signal on the low side on one of the legs of the bridge, in yello, and the current out of the current transformer (after the FW rectifier and the RC filter).
The bridge is driving a transformer that is loaded on the secondary.
As I adjust the potentiometer connected to the I sense of the 3843 the duty cycle is increased, this is good, but, at some point it will snap to 100% and the current wave form will drop in amplitude, so, it will start to run at 100% without regulation.
What I would like to have is smooth control from the low duty cycle to 99%
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Primary current sensing
