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4hv.org :: Forums :: High Voltage
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Where's my deadtime?!

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Dr. ISOTOP
Tue May 10 2011, 08:13AM Print
Dr. ISOTOP Registered Member #2919 Joined: Fri Jun 11 2010, 06:30PM
Location: Cambridge, MA
Posts: 652
I've been working on an SLR supply to charge my Marx; basically, a copy of Steve Ward's CCPS.
I've been running into an odd problem - my inverter output has no deadtime :(
The attached image shows Vce and Vge across one of the IGBTs (tall crappy signal is the gate voltage, smaller square signal is Vce). Scope is at 5V/div and 5uS/div. As you can see. the IGBT appears to be not turning off when the gate turns off.
I'm fairly certain that this is caused by sketchiness in the breadboard my logic lives on, and I'm somewhat less certain but still hopeful that putting the logic on an etched board will fix it, but before I do that, does anyone know why my IGBT's are doing this? Last time I checked, IGBT's should turn off when their gates are low tongue
The IGBT's are a fresh set, btw, so there should be nothing wrong with them.
1305015186 2919 FT0 Wtfbbqdeadtime
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Wolfram
Tue May 10 2011, 09:31AM
Wolfram Registered Member #33 Joined: Sat Feb 04 2006, 01:31PM
Location: Norway
Posts: 971
There's nothing wrong here. The IGBT actually switches off right after the gate voltage goes to zero, but at this point the tank current has crossed zero and is actually passing through the reverse diode in the IGBT. So the voltage you're seeing on the bridge output after the IGBT has turned off is actually supplied by the tank circuit and clamped to the DC bus voltage by the internal diode in the IGBT.


1305019864 33 FT115273 Halfres
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Dr. ISOTOP
Tue May 10 2011, 10:00PM
Dr. ISOTOP Registered Member #2919 Joined: Fri Jun 11 2010, 06:30PM
Location: Cambridge, MA
Posts: 652
I have no capacitor or transformer attached right now; this is the voltage across a single IGBT with an unloaded inverter.
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dude_500
Tue May 10 2011, 11:28PM
dude_500 Registered Member #2288 Joined: Wed Aug 12 2009, 10:42PM
Location: Cambridge, MA
Posts: 179
This wave makes perfect sense to me with no load on the inverter, in this case with absolutely nothing on the output, your effective output is the collector to emitter capacitance of the transistors. First the gates go high in one of the bridge conduction path, this output capacitive load is charged, all gates go low (dead time), the capacitor load is just sitting there, then the other conduction path closes, driving the capacitive load to the other polarity, the gates all go low and the capacitor is left untouched, etc repeating. If you put either the load on, or even a resistor (maybe a few hundred ohms or less for a big power resistor), it will bleed the transistor capacitance and you'll see a change in the waveform that should be expected. But this bridge bleeder is not necessary for normal operation, it's just to illustrate what's going on.
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