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parasole

Fri Nov 27 2015, 07:57AM

Registered Member #54647 Joined: Wed Mar 18 2015, 02:52PM
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Posts: 13

GeordieBoy wrote ...

Have you guys thought about using Direct Digital Synthesis (DDS) ?

You still will need a reliable frequency and phase measurement of resonant tank in order to adjust the DDS, this is the main challenge... Second challenge is output power regulation...

Wolfram

Fri Nov 27 2015, 12:29PM

Registered Member #33 Joined: Sat Feb 04 2006, 01:31PM
Location: Norway
Posts: 971

parasole wrote ...

You still will need a reliable frequency and phase measurement of resonant tank in order to adjust the DDS, this is the main challenge... Second challenge is output power regulation...

Agreed. These two were the main challenges I had during this project, everything else was pretty straightforward in comparison. I chose to do a plain analog + logic implementation for simplicity and ease of understanding, but the solutions I ended up with can also be implemented in an FPGA or a (fast enough) microcontroller.

For the phase detector, I had lots of trouble with XOR and edge detector ones, until I discovered this:

. After I implemented that one, I haven't had any problems (yet).

For the power control, I ended up with pulse density modulation with mains tracking. This control scheme has tons of benefits, like ZVS and near-ZCS under all loading conditions and perfect mains power factor. There are some excellent papers on this control scheme, particularly this

and this

I use the pulse density modulation to keep the inverter curent at a fixed fraction of the DC bus voltage. Changing this fraction changes the power level. Doing this ensures that the current draw is always proportional to bus voltage, so the power factor is perfect. The pulse density stays the same throughout the mains cycle, as long as the loading is the same. With no load placed in the coil, the power draw is low and dominated by resistive losses in the tank coil. As a load is placed in the coil, the pulse density increases and mains current draw increases, while the tank current stays constant. When the loading is so high that the pulse density becomes 100%, power throughput is at a maximum value. If the loading is increased further, tank current and mains current draw decreases again. If a tapped matching inductor or transformer is used, the loading level at which maximum power transfer happens can be changed.

Just another tool to keep in the box for when it might come in handy that I have found very effective. Analog Devices have some good App Notes on DDS for those interested.

Thanks for the insight, that's clever. At the frequencies I'm working with now it's not too critical, but this will be very useful as I go to higher frequencies. I notice that some of the common DDS chips from AD have the comparator built-in, so it should be pretty clean to implement as well.

Wolfram

Mon Dec 21 2015, 01:45AM

Registered Member #33 Joined: Sat Feb 04 2006, 01:31PM
Location: Norway
Posts: 971

My design has been split into two boards. In the previous revision I was running out of space on the 10x10 cm standard size for cheap PCBs, and these boards are so much cheaper than a larger form factor. I then realized that it makes a lot of sense to split up the design in two boards. One board is the control board, and the other board contains the bridge and everything else mains-connected. This will allow different bridges to be used with the same control board, so that a wide variety of power levels and frequencies can be accomodated by using different bridge boards. It will also allow the same bridges to be re-used if a new control board is made in the future.

For now I have started working on the control board, which is based on my old circuit but with a lot of improvements as outlined below. I have already completed one medium-power bridge board which is similar to my previous version, with the goal of delivering 4 kW at several hundred kilohertz. I will also make a second output board for driving IGBT bricks, for delivering tens of kilowatts at up to 100 kHz or so.

Here's a a screenshot of the 4 kW power board. The bridge thermal management is inpired by a design by Steve Ward which can be seen here:

A new phase detector has been implemented, as described in this thread:

. This has already been implemented in my prototype and it solved my earlier problems of occasional PLL lockup

The circuit has also been modified to provide a phase lead for the switching instead of a fixed phase shift. This has some advantages, as the PLL compensates for delays in the IGBTs and gate drivers. Since the delay is independent of the frequency now, it should give optimal switching over a wider frequency range.

The circuit for tank current phase sensing has been improved. With the new phase detector, primary current phase needs to be sensed accurately and the old circuit was simply not good enough. The new circuit has enough dynamic range to acquire lock at low input voltage while still working correctly with minimal dissipation at full power.

Tank current phase is now sensed separately from the bridge current. This allows my driver to work seamlessly with isolated and non-isolated LCLR as well as both transformer-coupled and non-isolated series resonant. This could be made to work in my old circuit as well, but with some compromises when running LCLR. The two dollars it costs for the second CT makes this a cheap and useful feature. The separate CTs also significantly improves the performance it is possible to get from the phase sensing CT.

The gate drive enable circuit for PDM has been revised. The old one had some trouble with glitches on the output due to differences in propagation delays between different logic paths, a classic race condition problem. The old circuit was based on disabling the gate drive signal with logic, as done in both the classic Ward and Conner *SSTC drivers, and this works perfectly most of the time. The problems were caused by my gate drivers, which react very fast. The 20 ns glitch pulses, which would never have made it through a classic GDT, triggered a dead-time period in my Silabs drivers. During this dead-time, the bridge output voltage naturally commutates towards the positive rail, but after the dead-time is over the low IGBT turns on again. This problem was solved by going for purely synchronous logic in the enable chain, costing a total of 20 cents in extra parts.

This scope shot (taken with a camera as I had no USB stick handy) shows the problem. The purple trace shows the bridge output current. The blue trace shows one of the bridge outputs. When the bottom IGBTs are turned on for pulse skipping, a small glitch gets through the enable gate due to a logic race condition. This triggers a dead-time period, where the bridge voltage commutates to the DC rail. When the dead-time is over, the lower IGBT turns on again and slams the output voltage to ground, generating some noise. The new solution avoids this by using synchronous logic

Steve Ward

Fri Dec 25 2015, 10:51PM

Registered Member #146 Joined: Sun Feb 12 2006, 04:21AM
Location: Austin Tx
Posts: 1055

Have you tried running that gate driver circuit without any negative bias on the gates? I've been tempted to do this for some time now, but i usually end up designing in some negative bias to be sure there won't be a problem, but this is costly as it requires an isolated supply for each transistor (at least i couldn't come up with a boot-strap solution). I'll be interested to see the results, perhaps you've already demonstrated that this drive scheme is fine and does not suffer from dv/dt induced gate turn on?

Wolfram

Tue Dec 29 2015, 06:03PM

Registered Member #33 Joined: Sat Feb 04 2006, 01:31PM
Location: Norway
Posts: 971

Steve Ward wrote ...

Have you tried running that gate driver circuit without any negative bias on the gates? I've been tempted to do this for some time now, but i usually end up designing in some negative bias to be sure there won't be a problem, but this is costly as it requires an isolated supply for each transistor (at least i couldn't come up with a boot-strap solution). I'll be interested to see the results, perhaps you've already demonstrated that this drive scheme is fine and does not suffer from dv/dt induced gate turn on?

Initially I wanted to see if I could get away with running without negative gate bias, and it worked so well that I've stuck with it through all revisions so far. Drain dV/dt is limited as I have soft switching in the bridge, but I don't notice any signs of dV/dt induced turn-on even when I adjust the switching phase angle so that I lose ZVS, apart from the regular miller plateu.

For the brick-driver add-on, I'm looking into using the MGJ2D-series of DC/DC converters from Murata, with a negative bias output, as I want to play it safe.

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